DS537 Datasheet, PDF (145/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
X-Ref Target - Figure 63
MPMC
MicroBlaze™
Processor
PLBV46
MDM
XPS CDMA XPS CDMA
Device Under
Test (DUT)
X-Ref Target - Figure 64
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
XPS LL
FIFO
DS537_63_091909
Figure 63: Spartan-6 FPGA System with the XPS LL TEMAC as the DUT
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
MicroBlaze™
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS537_64_091909
Figure 64: Spartan-3A DSP FPGA System with the XPS LL TEMAC as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 143.
Table 143: System Performance
Target FPGA
xc3sd3400a
xc6slx45t⁽¹⁾
xc4vfx60
Target F_MAX (MHz)
90
90
100
xc5vfx70t
120
xc6vlx240t
150
1. LUT utilization ~60%, BRAM utilization ~ 70%, I/O utilization ~80%
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
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