DS537 Datasheet, PDF (3/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
For more information on the Virtex-4, Virtex-5, and Virtex-6 FPGA Hard TEMAC silicon components, see the
UG074 Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide v1.9, UG194 Virtex-5 Embedded Tri-Mode Ethernet MAC
User Guide, and UG368 Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide. For more information on the soft
Tri Mode Ethernet MAC LogiCORE, see the UG138 LogicCORE Tri-Mode Ethernet MAC User Guide. For more
information on the Ethernet statistics LogiCORE, see the UG170 LogicCORE IP Ethernet Statistics User Guide. For
more information on the Ethernet AVB endpoint LogiCORE, please refer to the LogicCORE IP Ethernet AVB Endpoint
User Guide UG492.
The XPS_LL_TEMAC provides a standard PLB bus interface for a simple connection to PowerPC and MicroBlaze
processor cores to allow access to the registers.
Xilinx LocalLink 32-bit buses are provided for moving transmit and receive Ethernet data to and from the
XPS_LL_TEMAC. These buses are designed to provide direct connections to the built-in DMA function in some
Virtex-5 devices or may be used with a soft DMA IP core or any other custom logic in any supported device. The
LocalLink buses are designed to provide support for TCP/UDP partial checksum off load in hardware if that
function is required. The LocalLink buses will be described later in this document.
X-Ref Target - Figure 1
XPS LL TEMAC
PLB v46
(32 bits)
PLB v46
Slave
Local Link
(32 bits)
TX LLink
RX LLink
Shim
CSUM filter
buffer VLAN
Statistics
DCR
Registers
soft_temac_wrap
v6_temac_wrap
v5_temac_wrap
v4_temac_wrap
temac
Ethernet
Interface 0
MIIM0
MIIM1
Ethernet0
Ethernet1
Local Link
(32 bits)
TX LLink
RX LLink
CSUM filter
buffer VLAN
Ethernet
Interface 1
Clocking
MGTs IOBs
AVB0 AVB1
Figure 1: XPS_LL_TEMAC Block Diagram
DS537_01_091909
The XPS_LL_TEMAC provides basic interrupt generation and control with interrupt control registers. The interrupt
function will be described in more detail later in this document.
Support for many PHY interfaces is included and is selected with parameters at build time. The PHY interface
support varies based on the TEMAC type selected. Please refer to Table 1.
The MII interface is supported for 10 and 100 Mbs and the 1000 Base-X interface is support for 1000 Mbs. The
GMII/MII, RGMII v1.3, RGMII v2.0, and SGMII interfaces support all three speeds.
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