DS537 Datasheet, PDF (144/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
X-Ref Target - Figure 60
IXCL
DXCL
MPMC
MDM
XPS
CDMA
XPS
CDMA
Device Under
Test
MicroBlaze™
Processor
PLBV46
X-Ref Target - Figure 61
XPS
BRAM
XPS
INTC
XPS
GPIO
XPS UART
Lite
XPS LL
FIFO
DS537_60_091909
Figure 60: Virtex-6 FPGA System with the XPS LL TEMAC as the DUT
XCL
XCL
MPMC
XPS
CDMA
XPS
CDMA
XPS Device Under
BRAM
Test
MicroBlaze™
Processor
PLBV46
PowerPC 440
Processor
X-Ref Target - Figure 62
LMB
BRAM
MDM
XPS XPS UART
INTC
Lite
PPC440
MC DDR2
DS537_61_091909
Figure 61: Virtex-5 FPGA System with the XPS LL TEMAC as the DUT
PLBV46
PLBV46
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
DPLB0
PowerPC ^®405
Processor ^IPLB0
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
DS537_62_100909
Figure 62: Virtex-4 FPGA System with the XPS LL TEMAC as the DUT
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