DS537 Datasheet, PDF (50/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 27: TEMAC Ready Status Register Ethernet Interface 1 Bit Definitions (Cont’d)
Bit(s) Name
Core
Access
Reset
Value
Description
29 MIIM_WR
Read
MII Management Write Ready Interface 1. This bit is set (ready) when no MII
Management registers write operation is pending. Corresponds to
1
ADDRESS_CODE 0x3B4.
0 - a MIIM register write operation is in progress
1 - all pending MIIM write operations are complete
28
AF_RR
Read
Address Filter Read Ready Interface 1. This bit is set (ready) when no
address filter registers write operation is pending. Includes ADDRESS_CODE
1 ^{values of 0x380 - 0x390.}
0 - a address filter register write operation is in progress
1 - all pending address filter write operations are complete
27
AF_WR
Read
Address Filter Write Ready Interface 1. This bit is set (ready) when no
address filter registers write operation is pending. Includes ADDRESS_CODE
1
values of 0x380 - 0x390.
0 - a address filter register write operation is in progress
1 - all pending address filter write operations are complete
26 CFG_RR
Read
Configuration Register Read Ready Interface 1. This bit is set (ready) when
no configuration registers write operation is pending. Includes
1
ADDRESS_CODE values of 0x200 - 0x340.
0 - a configuration register write operation is in progress
1 - all pending configuration write operations are complete
25 CFG_WR
Read
Configuration Register Write Ready Interface 1. This bit is set (ready) when
no configuration registers write operation is pending. Includes
1
ADDRESS_CODE values of 0x200 - 0x340.
0 - a configuration register write operation is in progress
1 - all pending configuration write operations are complete
16 - 24 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always return
zero.
15
HARD_ACS
_RDY
Read
Hard register Access Ready Interface 1. This bit is set (ready) when all other
used bits in this Ready Status register are set.
1
0 - an access operation is in progress
1 - all pending access operations are complete
0 - 14 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always return
zero.
Indirectly Addressable TEMAC Registers
TEMAC Receive Configuration Word 0 (RCW0) Registers
The TEMAC Receive Configuration Word 0 Register is shown in Figure 29. There is a separate register for each of
the two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers. These registers can be written at any time but the receiver logic
will only apply the configuration changes during Inter Frame gaps.
X-Ref Target - Figure 29
31
0
PauseAddr(31:0)
DS537_29_091909
Figure 29: EMAC Receive Configuration Word 0 (RCW0) Registers (ADDRESS_CODE 0x200)
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