DS537 Datasheet, PDF (28/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Transmit Pause Frame Registers (TPF0 and RPF1)
The Transmit Pause Frame TEMAC 0 Register is shown in Figure 6. This register provides a value of pause when
enabled by the FCC register (page 54). When enabled, the Ethernet will transmit a pause frame whenever this
register is written. Pause values are defined in units of pause quanta which are defined as 512 bit times for the
current transmission speed. Therefore, pause times may have values ranging from 0 to 65,535 * 512 bit times. A
separate TPF register exists for TEMAC interface 0 and TEMAC interface 1.
X-Ref Target - Figure 6
16
31
Reserved
TPFV
DS537_06_091909
Figure 6: Transmit Pause Frame Registers (offset 0x004 and 0x044)
Table 10 shows the Transmit Pause Frame Register bit definitions.
Table 10: Transmit Pause Frame register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
16 - 31 TPFV
Read/Write
Transmit Pause Frame Value. These bits denote the value of the transmit
0x0
pause frame pause time in units of 512 bit times. If enabled by the FCC
register, writing a value into this register initiates the transmission of a single
pause frame with the pause value defined in this field.
0 - 15 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Transmit Inter Frame Gap Adjustment Registers (IFGP0 and IFGP1)
The Transmit Inter Frame Gap Adjustment Register is shown in Figure 7. This register provides a duration value of
Inter Frame Gap when enabled by the TC register (page 52). When enabled, the TEMAC will use the value of this
register to extend the Inter Frame Gap beyond the minimum of 12 idle cycles which is 96-bit times on the Ethernet
Interface. A separate IFGP register exists for TEMAC interface 0 and TEMAC interface 1.
X-Ref Target - Figure 7
24
31
Reserved
IFGP
DS537_07_091909
Figure 7: Transmit Inter Frame Gap Adjustment Registers (offset 0x008 and 0x048)
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