DS537 Datasheet, PDF (18/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 4: XPS_LL_TEMAC Design Parameters
Feature/Description
Parameter Name
Allowable Values
Default Values
VHDL
Type
Transmit VLAN stripping for C_TEMAC0_TXVLAN_STRP
TEMAC 0
1 = Tx VLAN stripping used
0 = Tx VLAN stripping unused
0
integer
Receive VLAN stripping for C_TEMAC0_RXVLAN_STRP
TEMAC 0
1 = Rx VLAN stripping used
0 = Rx VLAN stripping unused
0
integer
Transmit VLAN stripping for C_TEMAC1_TXVLAN_STRP
TEMAC 1
1 = Tx VLAN stripping used
0 = Tx VLAN stripping unused
0
integer
Receive VLAN stripping for C_TEMAC1_RXVLAN_STRP 1 = Rx VLAN stripping used
TEMAC 1
0 = Rx VLAN stripping unused
0
integer
Extended Multicast
address filtering for
TEMAC 0
C_TEMAC0_MCAST_EXTEND
1 = Extended multicast
filtering used
0 = Extended multicast
filtering unused
0
integer
Extended Multicast
address filtering for
TEMAC 1
C_TEMAC1_MCAST_EXTEND
1 = Extended multicast
filtering used
0 = Extended multicast
filtering unused
0
integer
Statistic gathering for
TEMAC 0
C_TEMAC0_STATS
1 = Statistics gathering used
0 = Statistics gathering
0
integer
unused
Statistic gathering for
TEMAC 1
C_TEMAC1_STATS
1 = Statistics gathering used
0 = Statistics gathering
0
integer
unused
Ethernet Audio Video
Bridging (AVB) mode for
TEMAC 0
C_TEMAC0_AVB
1 = Ethernet AVB mode used
0 = Ethernet AVB mode
0
unused
integer
Ethernet Audio Video
Bridging 1AVB) mode for
TEMAC 0
C_TEMAC1_AVB
1 = Ethernet AVB mode used
0 = Ethernet AVB mode
0
unused
integer
1. C_BASEADDR must start on an address boundary that is an integer multiple of 524,288 (512K). For example, valid settings are
0x00000000, 0x00080000, or 0x00180000 etc
2. The default value will insure that the actual value is set, i.e., if the value is not set, a compiler error will be generated. The address
range must be at least 0x00080000.
3. C_HIGHADDR is required to be at least C_BASEADDR + 524,287 in order to provide space for the 32-bit addresses used by the
registers and memory. For example: C_BASEADDR = 0x00000000, C_HIGHADDR = 0x0007FFFF.
4. These parameters are calculated and automatically assigned by the EDK XPS tools during the system creation process
5. For some combinations of PHY interfaces and device families, IDELAY primitives are used by the xps_ll_temac to help align the
receive data with the receive clock. When IDELAY primitives are used, a IDELAYCTRL primitive is also required. The
IDELAYCTRL primitive(s) must be located in the proper area in the silicon in order for it to be effective and this is accomplished by
adding constraints to the ucf-file. The method for setting the LOC constraint(s) is to use the C_IDELAYCTRL_LOC parameter. This
parameter when properly set will generate constraints in the xps_ll_temac core ucf-file. Note that if the LOC constraints are set in
the system top-level ucf-file, then this parameter has no effect because the constraints in the system top-level ucf-file override
those in lower level ucf-files. The syntax of the parameter value is IDELAYCTRL_XNYM where N and M are coordinates and
multiple entries are concatenated by - (i.e, dash). The following is an example of how the parameter might be set in the MHS file.
The X and Y values will be different for each implementation. Please refer to the device family User Guide for more information on
selecting the correct IDELAY Controller location.
6. The MII supports 10 Mb/S and 100 Mb/S Ethernet speeds. GMII, RGMII, and SGMII support 10 Mb/S, 100 Mb/S, and 1000 Mb/S
Ethernet speeds. 1000 BASE-X supports 1000 Mb/S. All PHY_TYPE values support full-duplex only (half-duplex is not
supported). Not all PHY types are supported for all TEMAC types. Please refer to Table 1.
7. The value “00000” is a broadcast PHY address and should not be used to avoid contention between the internal HARD_TEMAC
PHYs and the external PHY(s).
8. The maximum frame size must not exceed the memory size - 24 bytes. For a memory size of 4096, the maximum frame size is
4072 (4096 - 24).
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