DS537 Datasheet, PDF (16/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 4: XPS_LL_TEMAC Design Parameters
Feature/Description
Parameter Name
Allowable Values
Default Values
VHDL
Type
PLB Base Address ⁽¹⁾
C_BASEADDR
Valid PLB Address
0xFFFFFFFF ⁽²⁾
std_logic_
vector
PLB High Address⁽³⁾
C_HIGHADDR
Valid PLB Address
0x00000000⁽²⁾
std_logic_
vector
System Specified PLB Bus Implementation Parameters
PLB Data Bus Width⁽⁴⁾
PLB Address Bus Width⁽⁴⁾
Number of Masters⁽⁴⁾
C_SPLB_DWIDTH
C_SPLB_AWIDTH
C_SPLB_NUM_MASTERS
32
32
1-16
32
integer
32
integer
8
integer
Width of Master ID Bus⁽⁴⁾ C_SPLB_MID_WIDTH
roundup(log₂(C_SPLB_NUM
_MASTERS))
3
integer
Data width supported by C_SPLB_NATIVE_DWIDTH
32
this core
32
integer
Enable/Disable PLB Point C_SPLB_P2P
0
to Point connection mode
0
integer
Enable/Disable reduced C_BUS2CORE_CLK_RATIO 1 = internal clock equal to PLB
internal PLB clock usage
clock
2
2 = internal clock is 1/2 of PLB
clock (uses Core_Clk)
integer
Subfamily of FPGA device C_SUBFAMILY
selected when
applicable⁽⁴⁾
Valid device subfamilies
"FX"
string
User Specified TEMAC Implementation Parameters
Reserved
C_RESERVED
0
0
integer
Number of IDELAYCTRLs C_NUM_IDELAYCTRL
required⁽⁵⁾
0-16
0
Integer
Location of
IDELAYCTRLs⁽⁵⁾
C_IDELAYCTRL_LOC
Valid IDELAYCTRL Locations
""
String
FPGA Device Family
Selected⁽⁴⁾
C_FAMILY
virtex6, virtex5, virtex4,
qvirtex4, qrvirtex4,
spartan3e, aspartan3e,
spartan3a, aspartan3a,
spartan3an, spartan3adsp,
aspartan3adsp, spartan6
virtex5
string
Type of TEMAC selected C_TEMAC_TYPE
0 = Virtex 5 Hard
1 = Virtex 4 Hard
2 = Soft
3 = Virtex 6 Hard
0
integer
INCLUDE I/O and BUFGs
as needed for the PHY
interface selected
PHY Interface Type
C_INCLUDE_IO
C_PHY_TYPE⁽⁶⁾
1 = I/O included
0 = I/O not included
0 = MII
1 = GMII/MII
2 = RGMII V1.3
3 = RGMII v2.0
4 = SGMII
5 = 1000Base-X
1
integer
1
integer
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