DS537 Datasheet, PDF (63/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 40: Example of a Read from a Multicast Address Table Register
Register Access
Value
Activity
LSW1
Write
0x00830000
Write the information that will go into the Multicast Address Table Access Word 1
register for Ethernet interface 1 including the address of the Multicast Address
Table register we will read (3 in this case) and set the write enable bit to 1
CTL1
Write
0x0000838C
Initiate the write to the Multicast Address Table Access Word 1 register by setting
the write enable and providing the address for that indirectly addressed register
RDY1
Read
0x0001007F
or
0x00000077
Poll ready register for Ethernet interface 1 until we see 0x0001007F indicating
that the Address Filter register read access is complete
LSW1
Read
data word
Read the lower part of the multicast address that is in the Multicast Address Table
register we read
MSW1
Read
data word
Read the upper part of the multicast address that is in the Multicast Address Table
register we read
TEMAC Address Filter Mode (AFM) Registers
The TEMAC Address Filter Mode Register is shown in Figure 41. There is a separate register for each of the two
Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address
used to access the LSW and CTL registers.
X-Ref Target - Figure 41
31
PM
Reserved
DS537_41_091909
Figure 41: TEMAC Address Filter Mode Registers (ADDRESS_CODE 0x390)
Table 41 shows the TEMAC Address Filter Mode Registers bit definitions.
Table 41: TEMAC Address Filter Mode Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
Promiscuous Receive Address Mode Enable. When this bit is "1", the
receive address filtering is disabled and all destination addresses are
31
PM⁽¹⁾
Read/Write
0
accepted. When this bit "0", the receive address filtering is enabled.
0 - address filtering enabled
1 - address filtering disabled (all addresses accepted)
0 - 30 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
1. Extended Multicast Filtering require the promiscuous mode be enabled/ address filtering is disabled (1)
TEMAC Interrupt Status (TIS) Registers
The TEMAC Interrupt Status register is shown in Figure 42. There is a separate register for each of the two Ethernet
Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address used to
access the LSW and CTL registers.
The TEMAC Interrupt Status registers and Interrupt Enable registers are used as part of the overall
XPS_LL_TEMAC interrupt control (Figure 9).
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