DS537 Datasheet, PDF (122/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 111 shows the Hard TEMAC Internal SGMII PCS Management Loopback Control Register bit definitions.
Table 111: SGMII Management Loopback Control Register (Register 17) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
1 - 15 Reserved
Returns 0s
0 Always return zeros.
Loopback
0 ^Position
Read/Write
Loopback is enabled or disabled using register 0 bit 14.
0
0 - loopback (when enabled) occurs directly before the interface to the
RocketIO transceiver
1 - loopback (when enabled) occurs in the RocketIO transceiver
Virtex-4 Hard TEMAC Implementations
Introduction to Physical Interfaces
The Hard TEMAC silicon component in the Virtex-4 FPGA devices is independent of, and can connect to, any type
of physical layer device. The XPS_LL_TEMAC provides additional circuitry around the Hard TEMAC silicon
component to allow easy use of several common physical layer device interfaces.
The following are two types of physical layer interfaces:
• BASE-T provide a link between the XPS_LL_TEMAC and copper mediums. This functionality can be
provided in a XPS_LL_TEMAC system by connecting to external BASE_T PHY devices which are readily
available. This connection can be made using MII, GMII/MII, RGMII, and SGMII interfaces.
• Virtex-4 devices support GMII/MII at 3.3 V or lower.
• BASE-X provide a link between the XPS_LL_TEMAC and (usually) fiber optic mediums. The
XPS_LL_TEMAC system can provide this function at 1000 Mb/S (1000BASE-X) by using a RocketIO
transceiver.
Media Independent Interface (MII)
The Media Independent Interface (MII), defined in IEEE 802.3 clause 22, is a parallel interface that connects at
10-Mb/S and/or 100-Mb/S to external PHY devices.
Please refer to UG074 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide v1.9 for an equivalent diagram of
the clock management scheme when the XPS_LL_TEMAC parameter C_INCLUDE_IO = “1”. When the parameter
C_INCLUDE_IO = “0”, any BUFGs, IBUFGs, IBUFS, and OBUFs are not used. The MII design does not use clock
enables.
Virtex 4 Hard TEMAC MII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Gigabit Media Independent Interface (GMII)
The Gigabit Media Independent Interface (GMII), defined in IEEE 802.3 clause 35, is an extension of the MII used to
connect at 1-Gb/S to the PHY devices.
MII can be considered a subset of GMII, and as a result, GMII/MII together can carry Ethernet traffic at 10 Mb/S,
100 Mb/S, and 1 Gb/S.
When the GMII interface is selected with parameters for the XPS_LL_TEMAC, a GMII/MII interface is used which
is capable of all three Ethernet speeds.
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