DS537 Datasheet, PDF (5/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Some of the functions optionally provided by the XPS_LL_TEMAC are not compatible with other optional
functions. Figure 2 shows which optional functions are compatible with each other.
X-Ref Target - Figure 2
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Tx Csum Offload
Tx VLAN Tag
Tx VLAN Strp
Tx VLAN Trans
Rx Csum Offload
Rx VLAN Tag
Rx VLAN Strp
Rx VLAN Trans
Rx Multicast Fltr
Ethernet AVB
Statistics
NNNYYYYYY Y
N
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NY
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YYYY NNNYY Y
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YN Y
Y Y Y Y YY Y Y N Y
YN N N Y N N NN
Y
Y Y Y Y YY Y Y Y Y
DS537_02_091909
Figure 2: Option Function Compatibility
The XPS_LL_TEMAC provides one or two Ethernet interfaces. If two Ethernet interfaces are selected they are
completely independent except that they must use the same type of PHY interface.
Access to external PHY registers is provided via a standard MII Management bus. A separate Management bus is
provided for each of the Ethernet Interfaces. When using the SGMII or 1000 Base-X PHY interfaces, the
XPS_LL_TEMAC provides some PHY functionality and as a result also includes PHY registers which are also
accessible via the MII Management bus. These registers will be described later in this document.
This core optionally includes logic which helps calculate TCP/UDP checksums for transmit and verify TCP/UDP
checksums for receive. Using this logic can significantly increase the maximum Ethernet bus data rate while
reducing utilization of the processor for Ethernet tasks. Including the checksum off load function will increase the
amount of FPGA resources used for this core. The checksum information is included with each Ethernet frame
passing over the LocalLink bus interface. The checksum off load functionality can not be used at the same time as
the extended VLAN functionality.
The XPS_LL_TEMAC provides FIFO buffering of transmit and receive Ethernet frames allowing more optimal
transfer to and from the core with DMA. The number of frames that can be buffered in each direction is based on the
size of each frame and the size of the FIFOs which are selected by parameters at build time. If the XPS_LL_TEMAC
transmit FIFO becomes full it will throttle the transmit LocalLink interface until more room is available for Ethernet
frames. If the receive FIFO becomes full, frames will be dropped until more FIFO room is available. Receive frames
that do not meet Ethernet format rules or do not satisfy receive address qualification will always be dropped.
Optional logic can be included to facilitate handling of VLAN type frames. Auto insertion, stripping, or translation
of VLAN frames can be performed on transmit or receive with a number of options for choosing which frames will
be altered.
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