DS537 Datasheet, PDF (123/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Please refer to UG074 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide v1.9 for an equivalent diagram of
the clock management scheme when the XPS_LL_TEMAC parameter C_INCLUDE_IO = “1”. When the parameter
C_INCLUDE_IO = “0”, any BUFGs, IBUFGs, IBUFS, OBUFs, BUFGMUXs, and IDELAYs are not used. Independent
of the C_INCLUDE_IO parameter, a register stage has been inserted before the ODDR registers on the GMII_TXD,
GMII_TX_EN, and GMII_TX_ER signals.
Virtex 4 Hard TEMAC GMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Reduced Gigabit Media Independent Interface (RGMII)
The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the GMII/MII. RGMII achieves a
50% reduction in the pin count compared with GMII, and is therefore favored over GMII/MII by PCB designers.
This is achieved with the use of double-data-rate (DDR) flip-flops.
RGMII can carry Ethernet traffic at 10 Mb/S, 100 Mb/S, and 1 Gb/S.
For more information on RGMII, refer to the Hewlett-Packard RGMII Specification, version 2.0.
Please refer to UG074 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide v1.9 for an equivalent diagram of
the clock management scheme when the XPS_LL_TEMAC parameter C_INCLUDE_IO = “1” for both RGMII
Version 2.0 and RGMII Version 1.3. When the parameter C_INCLUDE_IO = “0”, the BUFG and IDELAY on the
RGMII_RXC signal are not used.
Virtex 4 Hard TEMAC RGMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Serial Gigabit Media Independent Interface (SGMII)
The Serial-GMII (SGMII) is an alternative interface to the GMII/MII that converts the parallel interface of the GMII
into a serial format. This radically reduces the I/O count and is therefore often favored by PCB designers. This is
achieved by using a RocketIO transceiver.
SGMII can carry Ethernet traffic at 10 Mb/S, 100 Mb/S, and 1 Gb/S.
The SGMII physical interface was defined by Cisco Systems. The data signals operate at a rate of 1.25 Gb/S.
Differential pairs are used to provide signal integrity and minimize noise. The sideband clock signals defined in the
specification are not implemented in the XPS_LL_TEMAC. Instead, the RocketIO MGT is used to transmit and
receive the differential data at the required rate using clock data recovery. For more information on SGMII, refer to
the Serial GMII Specification v1.7.
Please refer to the UG074 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide v1.9 for an equivalent diagram
of the clock management scheme.
Virtex 4 Hard TEMAC SGMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
SGMII Auto-Negotiation
The external SGMII capable PHY device performs auto negotiation with its link partner on the PHY Link (Ethernet
bus) resolving operational speed and duplex mode and then in turn performs a secondary auto negotiation with the
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