DS537 Datasheet, PDF (60/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
(C_TEMAC_TYPE = 0), and Virtex-6 hard TEMAC (C_TEMAC_TYPE = 3). After reset, a soft TEMAC
implementation will return 0xFFFFFFFF for all multicast address table entries while Virtex-4 hard TEMAC, Virtex-5
hard TEMAC and Virtex-6 hard TEMAC implementations will return 0x00000000 for all multicast address table
entries.
X-Ref Target - Figure 38
31
0
MulticastAddr(31:0)
DS537_38_091909
Figure 38: TEMAC Multicast Address Table Access Word 0 Registers (ADDRESS_CODE 0x388)
X-Ref Target - Figure 39
Multicast Address Table Access Word 1
Multicast Address Table Access Word 0
RSVD
RSVD ADDR MulticastAddr(47:32)
MulticastAddr(31:0)
47
00
01
10
11
Multicast Address Table
Multicast Address Register 0
Multicast Address Register 1
Multicast Address Register 2
Multicast Address Register 3
Figure 39: Multicast Address Table Diagram
0
DS537_39_091909
Table 37 shows the TEMAC Multicast Address Table Access Word 0 Registers bit definitions.
Table 37: TEMAC Multicast Address Table Access Word 0 Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 31 MulticastAddr Read/Write 0x0
Multicast Address (31:0). The multicast address bits are temporarily
deposited into this register for writing into a multicast address table register.
When a read from a multicast address table register has been performed,
the multicast address bits will be accessible from this register.
The address is ordered so the first byte transmitted/received is the lowest
positioned byte in the register; for example, a MAC address of
AA-BB-CC-DD-EE-FF would be stored in UnicastAddr(47:0) as
0xFFEEDDCCBBAA.
TEMAC Multicast Address Table Access Word 1 (MAW1) Registers
The TEMAC Multicast Address Table Access Word 1 Register is shown in Figure 40. There is a separate register for
each of the two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by
the address used to access the LSW and CTL registers.
The Multicast Addresses Table Access Word 0 and Word 1 registers combine to provide a 48 bit Ethernet addresses
to store in Multicast Address Table which can hold up to 4 addresses. These two registers also provide a place to
store addresses being read from the Multicast Address Table.
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