DS537 Datasheet, PDF (61/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Word 0 provides the low order 32 bits of the address while word 1 provides the high order 16 bits. Word 1 also
provides the table entry address and the read or write control signal. Figure 39 shows how word 0 and word 1
registers combine to make a Multicast Address Table entry.
X-Ref Target - Figure 40
RNW
ADDR
23
17 16 15
0
Reserved
Reserved
MulticastAddr(47:32)
DS537_40_091909
Figure 40: TEMAC Multicast Address Table Access Word 1 Registers (ADDRESS_CODE 0x38C)
Table 38 shows the TEMAC Multicast Address Table Access Word 1 Registers bit definitions.
Table 38: TEMAC Multicast Address Table Access Word 1 Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
24 - 31 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Multicast Address Table Register Read Enable. When this bit is "1", a
multicast address table register is read. When this bit is "0", a multicast
23
RNW
Read/Write
0
address table register is written.
0 - write operation
1 - read operation
18 - 22 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
16 - 17
ADDR
Read/Write
Multicast Address Table Register Address. This value is used to choose
the multicast address table register to access.
00 - multicast address table register 0
0x0 _{01 - multicast address table register 1}
10 - multicast address table register 2
11 - multicast address table register 3
0 - 15 MulticastAddr Read/Write
Multicast Address (47:32). The multicast address bits are temporarily
deposited into this register for writing into a multicast address table register.
When a read from a multicast address table register has been performed,
0x0 ^{the multicast address bits will be accessible from this register.}
The address is ordered so the first byte transmitted/received is the lowest
positioned byte in the register; for example, a MAC address of
AA-BB-CC-DD-EE-FF would be stored in UnicastAddr(47:0) as
0xFFEEDDCCBBAA.
Writing to the Multicast Address Table Registers
For writing to the desired multicast address table register, two write operations must be performed as follows:
1. Write to the LSW register (using the Ethernet interface 0 address or the Ethernet interface 1 address as
appropriate) with the value for the Multicast Address Table Access Word 0 [the multicast address (31:0) value].
2. Write to the CTL register (using the same Ethernet interface as in step 1) setting the write enable (WEN) bit and
providing ADDRESS_CODE 0x388. This is initiates a write to the Multicast Address Table Access Word 0
register.
3. Poll the RDY register for the Ethernet interface being accessed until the AF_WR bit is asserted or wait until the
HardAcsCmplt interrupt is asserted.
www.xilinx.com
61