DS537 Datasheet, PDF (24/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 8: XPS_LL_TEMAC PLB Indirectly Addressable TEMAC Registers (Cont’d)
Register Name
ADDRESS_CODE field of CTL0 or
CTL1 register (10 bits)
TEMAC0 or TEMAC1 Multicast Address Table
Access Word 1 Register (MAW1)
0x38C
TEMAC0 or TEMAC1 Address Filter Mode Register
(AFM)
0x390
TEMAC0 or TEMAC1 Interrupt Status Register (TIS)
0x3A0
TEMAC0 or TEMAC1 Interrupt Enable Register (TIE)
0x3A4
TEMAC0 or TEMAC1 MII Management Write Data
Register (MIIMWD)
0x3B0
TEMAC0 or TEMAC1 MII Management Access
Initiate Register (MIIMAI)
0x3B4
X-Ref Target - Figure 4
10-bit Indirect Access
Address
Register
0x000
0x02F
Unused
0x040
0x04F
Unused
TEMAC0 & TEMAC1
address
Direct Access
Register
0x200
TEMAC0
0x390 ^{configuration registers}
C_BASEADDR + 0x020
or
MSW
C_BASEADDR + 0X060
0x3A0
TEMAC0
TIS
C_BASEADDR + 0x024
or
LSW
C_BASEADDR + 0X064
C_BASEADDR + 0x028
or
CTL
C_BASEADDR + 0X068
C_BASEADDR + 0x02C RDY0
C_BASEADDR + 0x06C RDY1
0x3A4
ADDRESS
CODE
0x3B0
0x3B4
0x000
0x02F
TEMAC0
TIE
TEMAC0
MIIMWD
TEMAC0
MIIMAI
Unused
0x040
0x04F
Unused
0x200
TEMAC1
0x390 ^{configuration registers}
MII
Management
Interface
0x3A0
TEMAC1
TIS
0x3A4
TEMAC1
TIE
0x3B0
0x3B4
TEMAC1
MIIMWD
TEMAC1
MIIMAI
MII
Management
Interface
DS537_04_091909
Figure 4: Direct and Indirect Access TEMAC Registers Address Map
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
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