DS537 Datasheet, PDF (10/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

Table 3: I/O Signal Description
Signal Name
Temac1AvbTxClkEn
Temac1AvbRxClk
Temac1AvbRxClkEn
Avb2Mac1TxData
Avb2Mac1TxDataValid
Avb2Mac1TxUnderrun
Mac12AvbTxAck
Mac12AvbRxData
Mac12AvbRxDataValid
Mac12AvbRxFrameGood
Mac12AvbRxFrameBad
Temac12AvbTxData
Temac12AvbTxDataValid
Temac12AvbTxUnderrun
Avb2Temac1TxAck
Avb2Temac1RxData
Avb2Temac1RxDataValid
Avb2Temac1RxFrameGood
Avb2Temac1RxFrameBad
Core_Clk
TemacIntc0_Irpt
TemacIntc1_Irpt
TemacPhy_RST_n
LogiCORE IP XPS LL TEMAC (v2.03a)
Interface
AVB 1
AVB 1
AVB 1
AVB 1
AVB 1
Signal
Type
O
O
O
I
I
AVB 1
I
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
O
AVB 1
I
AVB 1
I
AVB 1
I
AVB 1
I
AVB 1
I
System Signals
Init
Status
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
System
I
System
O
0
System
O
0
Ethernet System Signals
Ethernet
O
0
Description
TEMAC to AVB Transmit Client
Clock Enable
TEMAC to AVB Receive Client Clock
TEMAC to AVB Receive Client Clock
Enable
AVB to TEMAC Transmit Data
AVB to TEMAC Transmit Data Valid
indicator
AVB to TEMAC Transmit Underrun
indicator
TEMAC to AVB Transmit
Acknowledge indicator
TEMAC to AVB Receive Data
TEMAC to AVB Receive Data Valid
indicator
TEMAC to AVB Receive Frame
Good indicator
TEMAC to AVB Receive Frame Bad
indicator
TEMAC to AVB Transmit Data
TEMAC to AVB Transmit Data Valid
indicator
TEMAC to AVB Transmit Underrun
indicator
AVB to TEMAC Transmit
Acknowledge indicator
AVB to TEMAC Receive Data
AVB to TEMAC Receive Data Valid
indicator
AVB to TEMAC Receive Frame
Good indicator
AVB to TEMAC Receive Data Frame
Bad indicator
1/2 frequency clock input derived
from SPLB_Clk used internally for
PLB accesses when
C_BUS2CORE_CLK_RATIO = 2
Interrupt indicator for TEMAC 0
Interrupt indicator for TEMAC 1
TEMAC to PHY reset signal
connected internally to the inverse of
the SPLB_Rst input. The PHY is
reset whenever the SPLB is reset
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