DS537 Datasheet, PDF (21/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 7: PLB Directly Addressable TEMAC Registers
Register Name
PLB Address
(offset from C_BASEADDR)
Access
Hard TEMAC 0 MSW Data Register (MSW0)⁽¹⁾
0x00000020
Read/Write
Hard TEMAC 0 LSW Data Register (LSW0)
0x00000024
Read/Write
Hard TEMAC 0 Control Register (CTL0)
0x00000028
Read/Write
Hard TEMAC 0 Ready Status (RDY0)
Hard TEMAC 1 MSW Data Register (MSW1)⁽¹⁾
0x0000002C
0x00000060
Read/
Read/Write
Hard TEMAC 1 LSW Data Register (LSW1)
0x00000064
Read/Write
Hard TEMAC 1 Control Register (CTL1)
0x00000068
Read/Write
Hard TEMAC 1 Ready Status (RDY1)
0x0000006C
Read
1. The MSW registers are used for reading from the Multicast Address Table as these reads can be 64-bits wide. All other
transactions only use the LSW registers.
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