DS537 Datasheet, PDF (40/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Please see the section on VLAN functions for more details (Extended VLAN Support, page 85).
X-Ref Target - Figure 20
Reserved
TransVlanVid
TagEnbl
18
29 30 31
StrpEnbl
DS537_20_091909
Figure 20: Transmit VLAN Table entry w/ all fields (offset 0x4000-0x7FFF and 0x44000-0x47FFF)
X-Ref Target - Figure 21
Reserved
TransVlanVid
Reserved
18
29 30 31
Reserved
DS537_21_091909
Figure 21: Transmit VLAN Table entry w/ one field (offset 0x4000-0x7FFF and 0x44000-0x47FFF)
Receive VLAN Data Table (0 and 1)
This table is used for data to support receive VLAN tagging, VLAN stripping, and VLAN translation. The table is
always 4K entries deep but the width depends on how many of the VLAN functions are included at build time.
VLAN translation requires 12 bits at each location while VLAN stripping and VLAN tagging require 1 bit each at
each location.
When all receive VLAN functions are included, the table is 14 bits wide. If VLAN functions are not included, the
bits for those functions will not be present and writes to those bits will have no effect while reads will return zero.
The table may be either 1-bit, 2-bits, 12-bits, 13-bits, or 14-bits wide depending on which features are present. The
table must be initialized by software via the PLB and is addressed on 32-bit word boundaries.
The receive VLAN Table entry with all VLAN functions present is shown in Figure 22 while Figure 23 shows the
receive VLAN Table entry with only the translation field. Note that the bit locations for the functions do not change
even when some functions are not used in the build.
Please see the section on VLAN functions for more details (Extended VLAN Support, page 85).
X-Ref Target - Figure 22
Reserved
TransVlanVid
TagEnbl
18
29 30 31
StrpEnbl
DS537_22_091909
Figure 22: Receive VLAN Table entry w/ all fields (offset 0x8000-0xBFFF and 0x48000-0x4BFFF)
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