DS537 Datasheet, PDF (34/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 14 shows the Interrupt Enable Register bit definitions.
Table 14: Interrupt Enable Register Bit Definitions
Bit(s)
Name
Core
Reset
Access Value
Description
Hard register Access Complete. This bit indicates that an access of the
TEMAC component has completed.
31 HardAcsCmplt Read/Write
0
0 - Hard register access is not complete
1 - Hard register access is complete
Auto Negotiation Complete. This bit indicates that auto negotiation of the
SGMII or 1000 Base-X interface has completed.
30
AutoNeg
Read/Write
0
0 - auto negotiation complete interrupt disabled
1 - auto negotiation complete interrupt enabled
Receive Complete. This bit indicates that a packet was successfully
received.
29
RxCmplt
Read/Write
0 _{0 - frame received interrupt disabled}
1 - frame received interrupt enabled
Receive Frame Rejected. This bit indicates that a receive frame was
rejected.
28
RxRject
Read/Write
0
0 - receive frame was rejected interrupt disabled
1 - receive frame was rejected interrupt enabled
Receive FIFO Overrun. This bit indicates that the receive FIFOs
overflowed while receiving an Ethernet frame.
27
RxFifoOvr Read/Write
0 _{0 - receive FIFO overflow occurred interrupt disabled}
1 - receive FIFO overflow occurred interrupt enabled
Transmit Complete. This bit indicates that a frame was successfully
transmitted.
26
TxCmplt
Read/Write
0
0 - frame transmitted interrupt disabled
1 - frame transmitted interrupt enabled
Receive DCM Lock. When using the soft TEMAC in a Spartan-3 device at
1000 Mbs, a DCM is used to phase-shift the PHY receive clock to align it
with the PHY receive data. This DCM requires a time period to lock to the
PHY receive clock whenever a reset or Ethernet speed change is made.
While the DCM is unlocked, the TEMAC is not able to receive Ethernet
25
RxDcmLock Read/Write
0 ^{frames. This interrupt bit will indicate when the DCM has locked to the PHY}
receive clock and normal Ethernet operation can take place. This bit will
always be one when using the hard TEMAC implementations or when using
the soft TEMAC in a device other than Spartan-3.
0 - Rx DCM not locked
1 - Rx DCM Locked
24
MgtRdy
Read
MGT Ready. This bit will indicate if the TEMAC is out of reset and ready for
use. In systems that use an MGT, this bit will go to ’1’ when the MGT is
ready to use. Prior to that time, access of TEMAC indirect access registers
0 ^{will not complete and the core will not operate. In systems that do not use}
an MGT, this signal will go to ’1’ immediately after reset.
0 - MGT / TEMAC not ready
1 - MGT / TEMAC ready
0 - 23 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Transmit VLAN Tag Register (TTAG0 and TTAG1)
The Transmit VLAN Tag Register is shown in Figure 12. This register is only used when the VLAN tagging is
included in the core at build-time (C_TEMACx_TXVLAN_TAG = 1). When a VLAN tag is added to a transmit
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