DS537 Datasheet, PDF (11/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

Table 3: I/O Signal Description
REFCLK⁽³⁾
Signal Name
DCLK
GTX_CLK_0⁽⁴⁾
MGTCLK_P
MGTCLK_N
MII_TXD_0(3:0)
MII_TX_EN_0
MII_TX_ER_0
MII_RXD_0(3:0)
MII_RX_DV_0
MII_RX_ER_0
MII_RX_CLK_0
MII_TX_CLK_0
LogiCORE IP XPS LL TEMAC (v2.03a)
Interface
Signal
Type
Init
Status
Ethernet
I
Ethernet
I
Ethernet
I
Ethernet
I
Ethernet
I
Ethernet Channel 0 MII Signals
Ethernet bus
0 MII
O
0
Ethernet bus
0 MII
O
0
Ethernet bus
0 MII
O
0
Ethernet bus
0 MII
I
Ethernet bus
0 MII
I
Ethernet bus
0 MII
I
Ethernet bus
0 MII
I
Ethernet bus
0 MII
I
Description
200 MHz input clock on global clock
routing used for signal delay
primitives for all GMII and RGMII
PHY modes, and when Ethernet
Statistics are enabled for all device
families other than Spartan-6
25 MHz to 50 MHz input clock on
global clock routing used for
dynamic reconfiguration for Virtex-4
hard TEMAC SGMII and 1000
Base-X PHY modes
125 MHz input clock on global clock
routing used to derive the other
transmit clocks for all GMII and
RGMII PHY modes. For soft TEMAC
MII PHY systems, this clock must be
driven by some clock (does not need
to be 125 MHz). The PLB clock may
be used in these cases. Also used
when Ethernet Statistics are enabled
with the Spartan-6 device family
Positive polarity of differential clock
used to drive RocketIO™ MGTs.
Must be connected to an external,
high-quality differential
reference clock of frequency of 125
MHz for Virtex-5 and 250 MHz for
Virtex-4.⁽⁵⁾
Negative polarity of differential clock
used to drive RocketIO MGTs.Must
be connected to an external,
high-quality differential
reference clock of frequency of 125
MHz for Virtex-5 and 250 MHz for
Virtex-4.⁽⁵⁾
TEMAC to PHY transmit data
TEMAC to PHY transmit enable
TEMAC to PHY transmit Error
enable
PHY to TEMAC receive data
PHY to TEMAC receive data valid
indicator
PHY to TEMAC receive error
indicator
PHY to TEMAC receive clock
PHY to TEMAC transmit clock (also
used for GMII/MII mode)
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