DS537 Datasheet, PDF (2/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Features (contd)
• Support for Pause frames for flow control
• Optional extended filtering for multicast frames
• Optional TX and RX statistics gathering
• Auto PAD and FCS field insertion or pass through on transmit
• Auto PAD and FCS field stripping or pass through on receive
• One or two full duplex Ethernet bus interfaces with a shared control interface and independent data and
interrupt interfaces
• Ethernet Audio Video Bridging (AVB) at 100/1000Mbs
How To Use This Document
Some of the information in this document is identical or very similar for all modes of the xps_ll_temac. The first
sections of this document will provide that information. In the cases where slight differences occur for a particular
mode, footnotes will be used to call attention to the variance.
Other information in this document is specific to either the type of TEMAC or PHY interface selected. Following the
sections containing the common information will be sections specific to Virtex-6 FPGA Hard TEMAC, Virtex-5
FPGA Hard TEMAC, Virtex-4 FPGA Hard TEMAC, and Soft TEMAC implementations.
Within these sections will be separate sections for each of the supported PHY interfaces.
Some users may wish to enjoy the entirety of this exciting document while others, more pressed for time, may wish
to refer only to the common information and the sections for the specific TEMAC type and PHY interface they will
be using.
Description
An XPS_LL_TEMAC provides additional functionality and ease of use to the Hard TEMAC silicon component that
is built into some Virtex6, Virtex-5 and Virtex-4 FPGA devices while providing a soft Ethernet MAC option for all of
the devices types that are supported. The main XPS_LL_TEMAC core uses several “helper” cores as needed for user
selected functions.
The soft TEMAC is based on the Xilinx Coregen Tri Mode Ethernet MAC LogiCORE™. The Virtex-6 FPGA TEMAC
is based on the Xilinx Coregen Virtex-6 Embedded Tri Mode Ethernet MAC LogiCORE. The Virtex-5 FPGA TEMAC
is based on the Xilinx Coregen Virtex-5 FPGA Embedded Tri Mode Ethernet MAC LogiCORE. The Virtex-4 FPGA
TEMAC is based on the Xilinx Coregen Virtex-4 FPGA Embedded Tri Mode Ethernet MAC LogiCORE. The
statistics function is based on the Xilinx Coregen Ethernet Statistics LogiCORE. The Ethernet AVB Endpoint is based
on the Xilinx Coregen Ethernet AVB Endpoint LogiCORE.
A high level block diagram of the XPS_LL_TEMAC IP core is shown in Figure 1. When the xps_ll_temac is used
with either the Virtex-6, Virtex-5 or Virtex-4 FPGA hard TEMAC modes, the core is free and does not require a
license.
When the xps_ll_temac is used with the soft TEMAC mode it will operate in an evaluation mode to allow users to
determine if they would like to purchase a license for the full version of the core.
During evaluation modes, the core is fully functional but will only operate for several hours before requiring a reset
to continue.
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