DS537 Datasheet, PDF (66/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 44: TEMAC Interrupt Enable Registers Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
Address Filter Write Interrupt Enable. This bit enables completion
interrupt for a write access of a multicast address table register.
27
AF WEN Read/Write
0
0 - no interrupt enabled
1 - interrupt enabled
Configuration Read Interrupt Enable. This bit enables completion
interrupt for a read access of a configuration register.
26
CFG REN Read/Write
0
0 - no interrupt enabled
1 - interrupt enabled
Configuration Write Interrupt Enable. This bit enables completion
interrupt for a write access of a configuration register.
25
CFG WEN Read/Write
0
0 - no interrupt enabled
1 - interrupt enabled
0 - 24 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Table 45 shows an examples of a Read and Set of the TEMAC Interrupt Enable Register.
Table 45: Example of a Read and Set of the TEMAC Interrupt Enable Register
Register Access
Value
Activity
CTL0
Write
0x000003A4
Initiate the read from the Interrupt Enable register by clearing the write enable and
providing the address for that indirectly addressed register
LSW0
Read
data word Read the current Interrupt Enable register value
LSW0
Write
0x0000007F
Write all ones in preparation for transferring it to the Interrupt Enable register thus
enabling all interrupts.
CTL0
Write
0x000083A4
Initiate the write to the Interrupt Enable register by setting the write enable and
providing the address for that indirectly addressed register
TEMAC MII Management Write Data (MIIMWD) Register
The TEMAC MII Management Write Data Register is shown in Figure 44. This register is shared between the two
Ethernet interfaces and is a temporary storage location for data to be written to a PHY register (internal or external)
via the MII Management interface. Only one register is needed for the two Ethernet interfaces because a PLB access
of a MII Management register can not be initiated until the previous access is complete (and, as a result, the register
is available for use). The MII Management write is initiated by writing to the MII Management Access Initiate
Register address after providing the data to this register and the PHY address and register address to the LSW
register.
This register is only used for writing to PHY registers. When reading from PHY registers, the data will be stored in
the LSW register. For more information on using the MII Management interface for accessing PHY registers, please
Using the MII Management to Access Internal or External PHY Registers, page 67.
X-Ref Target - Figure 44
16
31
Reserved
MiimWrData
DS537_44_091909
Figure 44: TEMAC MII Management Write Data Register (ADDRESS_CODE 0x3B0)
www.xilinx.com
66