DS537 Datasheet, PDF (64/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
X-Ref Target - Figure 42
CfgWst
MiimWst
AfWst
FabrRst
25 26 27 28 29 30 31
Reserved
CfgRst
Miimst
AfRst
DS537_42_091909
Figure 42: TEMAC Interrupt Status Registers (ADDRESS_CODE 0x3A0)
Table 42 shows the TEMAC Interrupt Status Registers bit definitions.
Table 42: TEMAC Interrupt Status Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
Fabric Read Interrupt Status. This bit indicates that a read access of a
fabric register has completed.
31
FABR RST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
MII Management Read Interrupt Status. This bit indicates that a read
access of a register using the MII management interface has completed.
30
MIIM RST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
MII Management Write Interrupt Status. This bit indicates that a write
access of a register using the MII management interface has completed.
29
MIIM WST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
Address Filter Read Interrupt Status. This bit indicates that a read access
of a multicast address table register has completed.
28
AF RST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
Address Filter Write Interrupt Status. This bit indicates that a write
access of a multicast address table register has completed.
27
AF WST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
Configuration Read Interrupt Status. This bit indicates that a read access
of a configuration register has completed.
26
CFG RST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
Configuration Write Interrupt Status. This bit indicates that a write
access of a configuration register has completed.
25
CFG WST Read/Write
0
0 - no interrupt pending
1 - interrupt pending
0 - 24 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
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