DS537 Datasheet, PDF (36/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
promiscuous address filtering mode. This register allows filtering of unicast frames not matching the address stored
in these registers. Please see the section on Extended Multicast Filtering for more information (Extended Multicast
Address Filtering Mode, page 80).
X-Ref Target - Figure 14
31
0
UnicastAddr(31:0)
DS537_14_091909
Figure 14: Unicast Address Word Lower Register (offset 0x030 and 0x070)
Table 17 shows the Unicast Address Word Lower Registers bit definitions.
Table 17: Unicast Address Word Lower Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
0 - 31 UnicastAddr Read/Write
0x00000000
Unicast Address (31:0). This address is used to match against the
destination address of any received frames.
The address is ordered so the first byte transmitted/received is the
lowest positioned byte in the register; for example, a MAC address
of AA-BB-CC-DD-EE-FF would be stored in UnicastAddr(47:0) as
0xFFEEDDCCBBAA.
Unicast Address Word Upper Register (UAWU0 and UAWU1)
The Unicast Address Word Upper Register is shown in Figure 15. This register and the previous register are only
used when extended multicast filtering is included in the core at build-time (C_TEMACx_MCAST_EXTEND = 1).
When using extended multicast filtering, the TEMAC core must be placed in promiscuous address filtering mode.
This register allows filtering of unicast frames not matching the address stored in these registers. Please see the
section on Extended Multicast Filtering for more information (Extended Multicast Address Filtering Mode,
page 80).
X-Ref Target - Figure 15
15
0
Reserved
UnicastAddr(47:32)
DS537_15_091909
Figure 15: Unicast Address Word Upper Register (offset 0x034 and 0x074)
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