DS537 Datasheet, PDF (117/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Additionally, these registers are directly involved in the operation of the SGMII auto negotiation function which
occurs between the XPS_LL_TEMAC and the external PHY device (typically a tri-speed BASE-T PHY).
These registers are accessed via the MII Management interface (see "Using the MII Management to Access Internal
or External PHY Registers" on page 67). These registers are only valid when using the SGMII PHY interface.
Table 99: Internal SGMII Management Registers
Register Name
SGMII Control Register (Register 0)
SGMII Status Register (Register 1)
SGMII PHY Identifier (Register 2 and 3)
SGMII Auto Negotiation Advertisement Register (Register 4)
SGMII Auto Negotiation Link Partner Ability Base Register (Register 5)
SGMII Auto Negotiation Expansion Register (Register 6)
SGMII Auto Negotiation Next Page Transmit Register (Register 7)
SGMII Auto Negotiation Next Page Receive Register (Register 8)
SGMII Extended Status Register (Register 15)
SGMII Vendor Specific Register: Auto Negotiation Interrupt Control Register
(Register 16)
SGMII Vendor Specific Register: Loopback Control Register (Register 17)
Register Address
(REGAD)
0
1
2,3
4
5
6
7
8
15
16
17
Table 100 shows the Hard TEMAC Internal SGMII PCS Management Control Register bit definitions.
Table 100: SGMII Management Control Register (Register 0) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
Reset
15
Read/Write
self clearing
0 - normal operation
0
1 - PCS/PMA reset
14 ^Loopback
Read/Write
0
0 - disable loopback mode
1 - enable loopback mode
Speed
13 Selection
(LSB)
Returns 0
Always returns 0 for this bit. Along with bit 6, speed selection of 1000 Mb/S
0 is identified.
Auto
12 Negotiation
Enable
Read/Write
0 - disable auto negotiation
1
1 - enable auto negotiation
Power Down Read/Write
11
When set to "1", the RocketIO MGT is placed in a low power state. This bit
requires a reset (bit 15) to clear.
0
0 - normal operation
1 - power down
10 ^Isolate
Read/Write
0
0 - normal operation
1 - electrically isolate the PHY
Restart Auto Read/Write
9 _{Negotiation self clearing}
0 - normal operation
0
1 - restart auto negotiation process
8 Duplex Mode Returns 1
1 Always returns 1 for this bit to disable COL test.
7 Collision Test Returns 0
0 Always returns 0 for this bit to signal full duplex mode.
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