DS537 Datasheet, PDF (104/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 77 shows the second Hard TEMAC Internal SGMII PCS Management PHY Identifier Register bit definitions.
Table 77: SGMII Management PHY Identifier (Register 3) Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
10 - 15
OUI
Read
returns OUI Organizationally Unique Identifier (OUI) from IEEE is 0x000A35.
(19-24) 0x0035
30
MMN
Returns 0
0
Manufacturer’s Model Number. Always returns 0s.
29
Revision
Returns 0
0
Revision Number. Always returns 0s.
Table 78 shows the Hard TEMAC Internal SGMII PCS Management Auto Negotiation Advertisement Register bit
definitions.
Table 78: SGMII Management Auto Negotiation Advertisement Register (Register 4) Bit Definitions
Bit(s)
Name
Core Access Reset Value
Description
0 - 15
All bits
Read
0x0001 SGMII defined value sent from the MAC to the PHY.
Table 79 shows the Hard TEMAC Internal SGMII PCS Management Auto negotiation Link Partner Ability Base
Register bit definitions.
Table 79: SGMII Management Auto negotiation Link Partner Ability Base Register (Register 5) Bit
Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
PHY Link Status
15
Read
This refers to the link status of the external PHY device with its Link
Partner across the PHY Link.
1
0 - link down
1 - link up
14 ^Acknowledge
Read
0
Used by the auto negotiation function to indicate reception of a link
partner’s base or next page.
13 Reserved
Returns 0
0 Always return zero.
Duplex Mode
12
Read
The resolved duplex mode that the external PHY device has auto
negotiated with its Link Partner across the PHY Link.
0
0 - half duplex
1 - full duplex
Speed
10 - 11
Read
The resolved operating speed that the external PHY device has auto
negotiated with its Link Partner across the PHY Link.
00 - 10 Mb/S
0x0 _{01 - 100 Mb/S}
10 -1000 Mb/S
11 - Reserved
1 - 9 Reserved
Returns 0s 0x0 Always return zeros.
0 Reserved
Returns 1
1 Always return one.
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