DS537 Datasheet, PDF (143/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 142: XPS_LL_TEMAC Spartan-3 FPGA Performance and Resource Utilization Benchmarks
Parameter Values
Device Resources
0
2048
0
0
0
0
0
2
2666
2707
4
3489
4
0
16384
0
0
0
0
0
2
2746
2780
18
3682
4
1
16384
0
0
0
0
0
2
5232
5196
36
7132
7
1
16384
1
0
0
0
0
2
5749
5784
36
7887
7
0
16384
1
0
0
0
0
2
2988
3071
18
4051
4
0
32768
0
0
0
0
0
2
2822
2804
34
3831
4
1
32768
0
0
0
0
0
2
5400
5250
68
7449
7
1
32768
1
0
0
0
0
2
5918
5842
68
8207
7
0
32768
1
0
0
0
0
2
3080
3098
34
4210
4
0
32768
1
0
0
0
1
2
3991
4104
36
4958
5
0
32768
1
0
0
1
1
2
4090
4198
38
5112
5
0
32768
0
0
1
1
1
2
4336
4376
42
5368
5
0
32768
0
1
1
1
1
2
4344
4378
46
5378
5
1
32768
0
1
1
1
1
2
8410
8399
92
10476
8
System Performance
To measure the system performance (F_MAX) of the XPS LL TEMAC core, it core was added to a Virtex-6 FPGA
system, a Virtex-5 FPGA system, a Virtex-4 FPGA system, a Spartan-6 FPGA system, and a Spartan-3A DSP FPGA
system as the Device Under Test (DUT) as shown in Figure 60, Figure 61, Figure 62, Figure 63, and Figure 64.
Because the XPS LL TEMAC core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When this core is combined with other designs in the system,
the utilization of FPGA resources and timing of the core design will vary from the results reported here.
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