DS537 Datasheet, PDF (32/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
The Interrupt Pending Register always represents the state of the Interrupt Status register bitwise ANDed with the
IE register. The Interrupt Pending Register is read only. In order to clear a bit in the Interrupt Pending Register,
either the corresponding bit must be cleared in either the Interrupt Status Register or the Interrupt Enable Register.
X-Ref Target - Figure 10
RxFifoOvr HardAcsCmplt
RxDcmLock _RxCmplt
24 25 26 27 28 29 30 31
Reserved
TxCmplt AutoNeg
MgtRdy
RxRject
DS537_10_091909
Figure 10: Interrupt Pending Registers (offset 0x010 and 0x050)
Table 13 shows the Interrupt Pending Register bit definitions.
Table 13: Interrupt Pending Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
31 HardAcsCmplt Read/Write
Hard register Access Complete. This bit indicates that an access of the
TEMAC component has completed.
0
0 - Hard register access is not complete
1 - Hard register access is complete
30
AutoNeg
Read
Auto Negotiation Complete Ethernet. This bit indicates that auto
negotiation of the SGMII or 1000 Base-X interface has completed.
0
0 - auto negotiation no complete
1 - auto negotiation complete
29
RxCmplt
Read
Receive Complete. This bit indicates that a packet was successfully
received.
0
0 - no frame received
1 - frame received
28
RxRject
Read
Receive Frame Rejected. This bit indicates that a receive frame was
rejected.
0
0 - no receive frame rejected
1 - receive frame was rejected
27
RxFifoOvr
Read
Receive FIFO Overrun. This bit indicates that the receive FIFOs
overflowed while receiving an Ethernet frame.
0
0 - normal operation, no overflow occurred
1 - receive FIFO overflow occurred and data was lost
26
TxCmplt
Read
Transmit Complete. This bit indicates that a frame was successfully
transmitted.
0
0 - no frame transmitted
1 - frame transmitted
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