DS537 Datasheet, PDF (69/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 48: Example of a PHY Register Read via the MII Management Interface
Register Access
Value
Activity
LSW1
Write
0x000000AF
Write the PHYAD (5 in this case) and REGAD (15 in this case) to the LSW register
for Ethernet interface 1.
CTL1
Write
0x000003B4
Initiate the read from the MII Management Access Initiate register by clearing the
write enable and providing the address for that indirectly addressed register. This
will start the transaction on the MII Management Interface to the PHY.
RDY1
Read
0x0001007F
or
0x0000007D
Poll ready register for Ethernet interface 1 until we see 0x0001007F indicating
that the MII Management Interface write access is complete.
LSW1
Read
data word Read the data value received from the PHY register.
Including or Excluding I/O in the Physical Interfaces
In order to allow the XPS_LL_TEMAC to be easy to use, the core includes BUFG, IBUFG, IBUF, OBUF and other
FPGA resources to correctly connect the external interface signals to the FPGA I/O.
Some users may find that this prevents them from being able to make custom connections on these signals which
may be required for their system. By setting the parameter C_INCLUDE_IO to “0”, these resources will not be
automatically provided. In this case the user will be responsible for making the appropriate connections.
TCP/UDP Checksum Off Load in Hardware
When using TCP or UDP Ethernet protocols, data integrity is maintained by calculating and verifying checksum
values over the TCP and UDP frame data. Normally this checksum functionality is handled by the protocol stack
software which can be relatively slow and use significant processor utilization for large frames at high Ethernet data
rates.
An alternative is to off load some of this transmit checksum generation and receive checksum verification in
hardware. This is possible by including checksum off loading in the XPS_LL_TEMAC using parameters. Including
the checksum off load functions are a trade off between using more FPGA resources and getting higher Ethernet
performance while freeing up processor use for other functions.
When using the TCP/UDP checksum off load function, checksum information is passed between the software and
the XPS_LL_TEMAC by using the header and footer fields in the transmit and receive LocalLink data interface
frames. Table 49, Table 50, Table 51, and Table 55 show the checksum off load fields.
The use of the TCP / UPD checksum off load function requires that the core connected to the XPS_LL_TEMAC via
the LocalLink also supports the LocalLink header and footer fields. While any custom core may be created to source
and sink data on the LocalLink, the cores provided by Xilinx at the time of the writing of this data sheet include the
XPS_LL_FIFO_V1_02_A (which does not support these LocalLink fields), the SDMA_v2_00_B which is part of the
MPMC_V5_04_A and the Hard DMA included in the PowerPC 440 Processor block (both of which do support these
LocalLink fields). Please refer to the Mapping Xilinx DMA Buffer Descriptor Fields to LocalLink Fields, page 74
section for more information.
TX_CSBEGIN is the beginning offset which points to the first byte that needs to be included in the checksum
calculation. The first byte is indicated by a value of zero. The beginning position must be 16 bit aligned. With TCP
and UDP you would want to set this value to skip over the Ethernet frame header as well as the IP datagram header
so that the checksumming is started in the proper place in the TCP or UDP segment. Operating systems may
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