DS537 Datasheet, PDF (92/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
C_INCLUDE_IO = “1”. When the parameter C_INCLUDE_IO = “0”, any BUFGs, IBUFGs, IBUFS, and OBUFs are
not used.
Virtex 6 Hard TEMAC MII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Gigabit Media Independent Interface (GMII)
The Gigabit Media Independent Interface (GMII), defined in IEEE 802.3 clause 35, is an extension of the MII used to
connect at 1-Gb/S to the PHY devices.
MII can be considered a subset of GMII, and as a result, GMII/MII together can carry Ethernet traffic at 10 Mb/S,
100 Mb/S, and 1 Gb/S.
When the GMII interface is selected with parameters for the XPS_LL_TEMAC, a GMII/MII interface is used which
is capable of all three Ethernet speeds.
The GMII design uses clock enables. Please refer to UG368 Virtex-6 Embedded Tri-Mode Ethernet MAC User Guide
for an equivalent diagram of the clock management scheme when the XPS_LL_TEMAC parameter
C_INCLUDE_IO = “1”. One modification has been performed to the receive clock when C_INCLUDE_IO = 1. The
XPS_LL_TEMAC design has been modified such that GMII_RX_CLK_0 is not connected to an IODELAY element.
It connects directly to the BUFIO and BUFR. This also applies to GMII_RX_CLK_1 when
C_TEMAC1_ENABLED=1. When the parameter C_INCLUDE_IO = “0”, any IBUFGs, IBUFS, OBUFs, BUFGMUXs,
BUFIOs, BUFRs, and IODELAYs are not used.
Virtex 6 Hard TEMAC GMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Reduced Gigabit Media Independent Interface (RGMII)
The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the GMII/MII. RGMII achieves a
50% reduction in the pin count compared with GMII, and is therefore favored over GMII/MII by PCB designers.
This is achieved with the use of double-data-rate (DDR) flip-flops.
RGMII can carry Ethernet traffic at 10 Mb/S, 100 Mb/S, and 1 Gb/S.
For more information on RGMII, refer to the Hewlett-Packard RGMII Specification, version 1.3 and 2.0.
The RGMII design uses clock enables. Please refer to UG368 Virtex-6 Embedded Tri-Mode Ethernet MAC User
Guide for an equivalent diagram of the clock management scheme when the XPS_LL_TEMAC parameter
C_INCLUDE_IO = “1” for both RGMII Version 2.0 and RGMII Version 1.3. When the parameter C_INCLUDE_IO =
“0”, the BUFR, BUFIO and IODELAY on the RGMII_RXC signal are not used.
Virtex 6 Hard TEMAC RGMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Serial Gigabit Media Independent Interface (SGMII)
The Serial-GMII (SGMII) is an alternative interface to the GMII/MII that converts the parallel interface of the GMII
into a serial format. This radically reduces the I/O count and is therefore often favored by PCB designers. This is
achieved by using a RocketIO transceiver.
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