DS537 Datasheet, PDF (67/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 46 shows the TEMAC MII Management Write Data Register bit definitions.
Table 46: TEMAC MII Management Write Data Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
16 - 31 MiimWrData Read/Write
0x0
MII Management Write Data. This field temporarily holds data to be written
to a PHY register.
0 - 15 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
TEMAC MII Management Access Initiate (MIIMAI) Register
The TEMAC MII Management Access Initiate Register is not actually a register at all. A write to this address
location initiates a MII Management write or read access to a PHY register either internal or external to the
XPS_LL_TEMAC. No data is actually stored at this address.
During a write operation the data in the LSW register is used to address the PHY and the PHY register. The MII
Management Write Data register holds the data that is written to the PHY register. During a read operation the LSW
register is used to address the PHY and the PHY register and the data from the PHY register is stored back in the
LSW register.
Using the MII Management to Access Internal or External PHY Registers
The MII Management interface is used to access PHY registers either in devices external to the FPGA or, in the case
of SGMII or 1000BASE-X PHYs, PHY registers internal to the Hard TEMAC silicon component as described in
Internal 1000BASE-X PCS/PMA Management Registers, page 110 and "Internal SGMII Management Registers,".
Prior to any MII Management accesses taking place, the Management Configuration register must be written with
a valid CLOCK_DIVIDE value and the MDIOEN bit must be set.
The determination as to which PHYs registers are accessed is by the value of the PHY_ADDR field. Each PHY,
internal or external, should have a unique 5-bit PHY address excluding "00000" which is define as a broadcast PHY
address.
The MII Management interface is defined in IEEE Std 802.3, Clause 22 as a two-wire interface with a shared
bi-directional serial data bus and a clock with a maximum permitted frequency of 2.5 MHz. As a result, MII
Management access can take many PLB clock cycles to complete.
To write to a PHY register, the data must be written to the MII Management Data register. The PHY address and
register number are written to the LSW register. Writing to the MII Management Access Initiate register address
starts the operation. The format of the PHYAD and REGAD in the LSW register is shown in Figure 45.
To read from a PHY register, the PHY address and register number are written to the LSW register. Writing to the
MII Management Access Initiate register address starts the operation. When the operation completes, the PHY
register value is available in the LSW register.
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