DS537 Datasheet, PDF(80/148 Page) Xilinx, Inc

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DS537 Datasheet, PDF (80/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

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LogiCORE IP XPS LL TEMAC (v2.03a)

X-Ref Target - Figure 50

Check Destination Address

field of received frame

AFM

bit

31 ="0" Is

address

filltering

enabled?

False

True

pause

frame

False

address

True

FCC

bit

="1"

pause

1 of 4

multicast

addresses

False True

enabled

True

CR bit

="0"

Are

multicast

frames

enabled?

frame

and pause,

but don't

pass frame

to user

True

Frame

Is it a

multicast

False

address?

True

False

broadcast

address

False

True

Reject

Frame

bit

="0"

Are

broadcast

frames

enabled

True

Frame

Is it a

broadcast

address?

False it must be a

unicast address

True

Frame

False

unicast

address

False

True

Reject

Frame

Is it

a pause

control frame

False

Type

field?

Reject

Frame

True

Frame

FCC

bit

="1"

pause

enabled

True

False

Frame

frame

and pause,

but don't

pass frame

to user

DS537_50_091909

Figure 50: Receive Address Basic Filtering Flow

Extended Multicast Address Filtering Mode

General

Currently the hard TEMAC core provides up to 4 multicast addresses that may be specified for receive address

validation (i.e., if an incoming multicast frameâs receive address matches one of the 4 specified addresses, it is

accepted). Some users require the ability to use many more multicast address values to filter receive addresses.

While this could be supported with promiscuous mode and software application filtering, some degree of hardware

off loading is desired to reduce processor utilization.

Including extended multicast address filtering at build-time by setting parameters C_TEMACx_MCAST_EXTEND

to 1 provides additional logic for address filtering beyond what is built in to the TEMAC core itself.

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