DS537 Datasheet, PDF (48/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
TEMAC Ready Status Register Ethernet Interface 0 (RDY0)
The Ready Status Register is shown in Figure 27. This register is read only. The bits in the RDY register are asserted
when there is no access in progress. When an access is in progress, a bit corresponding to the type of access is
automatically de-asserted. The bit is automatically re-asserted when the access is complete.
X-Ref Target - Figure 27
HARD_ACS_RDY
AF_WR FABR_RR
CFG_WR
MIIM_WR
15
25 26 27 28 29 30 31
Reserved
Reserved
CFG_RR
MIIM_RR
AF_RR
DS537_27_091909
Figure 27: TEMAC Ready Status Register Ethernet Interface 0 (offset 0x02C)
Table 26 shows the TEMAC Ready Status Register Ethernet Interface 0 bit definitions.
Table 26: TEMAC Ready Status Register Ethernet Interface 0 Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
31
FABR_RR
Read
Fabric Read Ready Interface 0. This bit is set (ready) when no fabric
based registers read operation is pending. Includes ADDRESS_CODE
values of 0x000 - 0x02F and 0x040 - 0x04F. These address ranges are
1
not currently supported.
0 - a fabric register read operation is in progress
1 - all pending fabric read operations are complete
30
MIIM_RR
Read
MII Management Read Ready Interface 0. This bit is set (ready) when
no MII Management registers read operation is pending. Corresponds to
1 ^{ADDRESS_CODE 0x3B4.}
0 - a MIIM register read operation is in progress
1 - all pending MIIM read operations are complete
29
MIIM_WR
Read
MII Management Write Ready Interface 0. This bit is set (ready) when
no MII Management registers write operation is pending. Corresponds
1 ^{to ADDRESS_CODE 0x3B4.}
0 - a MIIM register write operation is in progress
1 - all pending MIIM write operations are complete
28
AF_RR
Read
Address Filter Read Ready Interface 0. This bit is set (ready) when no
address filter registers write operation is pending. Includes
1 ^{ADDRESS_CODE values of 0x380 - 0x390.}
0 - a address filter register write operation is in progress
1 - all pending address filter write operations are complete
27
AF_WR
Read
Address Filter Write Ready Interface 0. This bit is set (ready) when no
address filter registers write operation is pending. Includes
1 ^{ADDRESS_CODE values of 0x380 - 0x390.}
0 - a address filter register write operation is in progress
1 - all pending address filter write operations are complete
26
CFG_RR
Read
Configuration Register Read Ready Interface 0. This bit is set (ready)
when no configuration registers write operation is pending. Includes
1 ^{ADDRESS_CODE values of 0x200 - 0x340.}
0 - a configuration register write operation is in progress
1 - all pending configuration write operations are complete
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