DS537 Datasheet, PDF (131/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 121 shows the Hard TEMAC Internal 1000BASE-X PCS/PMA Management Auto Negotiation Next Page
Receive Register bit definitions.
Table 121: 1000BASE-X Management Auto Negotiation Next Page Receive Register (Register 8) Bit
Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
15
Next Page
Read
0
0 - last page
1 - additional next page(s) will follow
14
Acknowledge
Read
0
Used by auto negotiation function to indicate reception
of a link partner’s base or next page.
13
Message Page
Read
0
0 - unformatted page
1 - message page
12
Acknowledge 2
Read
0 - cannot comply with message
0
1 - complies with message
11
Toggle
Read
0
Value toggles between sequent pages.
0 -10
Message or unformatted
Code Field
Read
0x0 (null
Message code field or unformatted page encoding as
message code) dictated by bit 13.
Table 122 shows the Hard TEMAC Internal 1000BASE-X PCS/PMA Management Extended Status Register bit
definitions.
Table 122: 1000BASE-X Management Extended Status Register (Register 15) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
15
1000BASE-X
Full Duplex
Returns 1
1
Always returns a 1 for this bit because 1000BASE-X full duplex is
supported.
14
1000BASE-X
Half Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-X half duplex is not
supported.
13
1000BASE-T
Full Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-T full duplex is not
supported.
12
1000BASE-T
Half Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-T half duplex is not
supported.
0 - 11
Reserved
Returns 0s 0x0 Always return zeros.
Table 123 shows the Hard TEMAC Internal 1000BASE-X PCS/PMA Management Auto Negotiation Interrupt
Control Register bit definitions.
Table 123: 1000BASE-X Management Auto Negotiation Interrupt Control Register (Register 16) Bit
Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
2 - 15 Reserved Returns 0s
0 Always return zeros.
If the interrupt is enabled, this bit will be asserted upon the completion of an
auto negotiation cycle; it will only be cleared by writing 0 to this bit. If the
1
Interrupt
Status
Read/Write
interrupt is disabled, this bit will be set to 0. This is the auto negotiation
0
complete interrupt.
0 - interrupt is asserted
1 - interrupt is not asserted
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