DS537 Datasheet, PDF (33/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 13: Interrupt Pending Register Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
25
RxDcmLock
Read
Receive DCM Lock. When using the soft TEMAC in a Spartan-3 device at
1000 Mbs, a DCM is used to phase-shift the PHY receive clock to align it
with the PHY receive data. This DCM requires a time period to lock to the
PHY receive clock whenever a reset or Ethernet speed change is made.
While the DCM is unlocked, the TEMAC is not able to receive Ethernet
0 ^{frames. This interrupt bit will indicate when the DCM has locked to the PHY}
receive clock and normal Ethernet operation can take place. This bit will
always be one when using the hard TEMAC implementations or when using
the soft TEMAC in a device other than Spartan-3.
0 - Rx DCM not locked
1 - Rx DCM Locked
24
MgtRdy
Read
MGT Ready. This bit will indicate if the TEMAC is out of reset and ready for
use. In systems that use an MGT, this bit will go to ’1’ when the MGT is
ready to use. Prior to that time, access of TEMAC indirect access registers
0 ^{will not complete and the core will not operate. In systems that do not use}
an MGT, this signal will go to ’1’ immediately after reset.
0 - MGT / TEMAC not ready
1 - MGT / TEMAC ready
0 - 23 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Interrupt Enable Registers (IE0 and IE1)
The Interrupt Enable Register is shown in Figure 11. This register combined with the IS, IP, TIS, and TIE registers
define the interrupt interface of the XPS_LL_TEMAC. The Interrupt Enable register uses one bit to represent each
XPS_LL_TEMAC internal interruptible condition represented in the Interrupt Status Register. A separate IE register
exists for TEMAC interface 0 and TEMAC interface 1.
Each bit set in the Interrupt Enable Register allows an interruptible condition bit in the Interrupt Status Register to
pass through to the Interrupt Pending Register.
X-Ref Target - Figure 11
RxFifoOvr HardAcsCmplt
RxDcmLock _RxCmplt
24 25 26 27 28 29 30 31
Reserved
TxCmplt AutoNeg
MgtRdy
RxRject
DS537_11_091909
Figure 11: Interrupt Enable Registers (offset 0x014 and 0x054)
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