DS537 Datasheet, PDF (19/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Allowable Parameter Combinations
Please refer to Table 1, Table 2, and Figure 2 for parameter combination restrictions.
Parameter - Port Dependencies
The Parameter-Port dependencies are shown in the Table 5.
Table 5: XPS_LL_TEMAC Parameter-Port Dependencies
Generic
or Port
Name
Affects
Depends
Design Parameters
C_TEMAC1_ENABLED
G1
G2 - G15
G2
C_TEMAC1_PHYADDR
G1
G3
C_TEMAC1_TXFIFO
G1
G4
C_TEMAC1_RXFIFO
G1
G5
C_TEMAC1_TXCSUM
G1
G6
C_TEMAC1_RXCSUM
G1
G7
C_TEMAC1_TXVLAN_TAG
G1
G8
C_TEMAC1_RXVLAN_TAG
G1
G9
C_TEMAC1_TXVLAN_TRAN
G1
G10 C_TEMAC1_RXVLAN_TRAN
G1
G11 C_TEMAC1_TXVLAN_STRP
G1
G12 C_TEMAC1_RXVLAN_STRP
G1
G13 C_TEMAC1_MCAST_EXTEND
G1
G14 C_TEMAC1_STATS
G1
G15 C_TEMAC1_AVB
G1
Relationship Description
If C_TEMAC1_ENABLED is "1" then G2
through G15 values will be used. If
C_TEMAC1_ENABLED is "0" then the values
of G2 through G15 are ignored.
Memory and Register Descriptions
The XPS_LL_TEMAC contains memory and addressable registers for read/write operations as shown in Table 6,
Table 7, and Table 8 and as shown in Figure 3 (The internal PHY registers will be discussed in greater detail later in
this document). The memory map is divided into three types:
1. Memory and registers located in soft logic which are directly addressable via the PLB bus (referred to as
memory and soft registers).
2. Registers located in the Hard Silicon TEMAC or the soft TEMAC component which are directly addressable via
the PLB bus (referred to as TEMAC direct registers). Three of the four registers (MSW, LSW, CTL) are shared
between the two Ethernet interfaces but are accessible from separate addresses for each Ethernet interface. For
example, The CTL register is accessible from PLB baseaddr offset 0x028 and also from 0X068. There are separate
RDY registers for each Ethernet Interface.
3. Registers located in the Hard Silicon TEMAC or the soft TEMAC component which are indirectly addressable,
internal or external PHY device registers connected to the MII management interface, all of which are
addressed indirectly through the registers of type 2 above (these are referred to as TEMAC indirect registers).
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