DS537 Datasheet, PDF (6/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Additional logic may be selected to provide additional filtering of receive frames with multicast destination
addresses. The XPS_LL_TEMAC provides native support for up to 4 multicast addresses and the optional enhanced
logic can support many more.
Logic may be selected to gather statistics on transmit and receive frames. This logic provides 64-bit counters for
many statistics about the frames passing through the TEMAC core.
Support from Ethernet AVB may be included in the design. Ethernet AVB only supports Ethernet speeds of 100Mbs
and 1000Mbs.
I/O Signals
The XPS_LL_TEMAC signals are listed and described in Table 3.
Table 3: I/O Signal Description
Signal Name
SPLB_Clk
SPLB_Rst⁽¹⁾
PLB_ABus(0:31)
PLB_PAValid
PLB_masterID(0:C_SPLB_MID_WIDTH-1)
PLB_RNW
PLB_BE(0:(C_SPLB_DWIDTH/8)-1)
PLB_size(0:3)
PLB_type(0:2)
PLB_wrDBus(0:C_SPLB_DWIDTH-1)
Sl_addrAck
Sl_SSize(1:0)
Sl_wait
Sl_rearbitrate
Sl_wrDack
Sl_wrComp
Interface
Signal
Type
Init
Status
TEMAC PLB Slave Signals
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
Sl_rdBus(0:C_SPLB_DWIDTH-1)
Sl_rdDAck
Sl_rdComp
PLB
O
0
PLB
O
0
PLB
O
0
Sl_MBusy(0:C_SPLB_NUM_
MASTERS-1)
Sl_MWrErr(0:C_SPLB_NUM_
MASTERS-1)
SlMRdErr(0:C_SPLB_NUM_
MASTERS-1)
PLB
O
0
PLB
O
0
PLB
O
0
Unused PLB Slave Signals
Description
PLB Clock
PLB Reset
PLB address bus
PLB primary address valid indicator
PLB requesting master identification
PLB read not write
PLB byte enables
PLB transfer size
PLB transfer type
PLB write data bus
Slave address acknowledge
Slave data bus size
Slave wait indicator
Slave rearbitrate bus indicator
Slave write data acknowledge
Slave write transfer complete
indicator
Slave read bus
Slave read data acknowledge
Slave read transfer complete
indicator
Slave busy indicator (1 bit for each
PLB master)
Slave write error indicator (1 bit for
each PLB master)
Slave read error indicator (1 bit for
each PLB master)
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