DS537 Datasheet, PDF (137/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 136 shows the Hard TEMAC Internal SGMII PCS Management Auto Negotiation Interrupt Control Register
bit definitions.
Table 136: SGMII Management Auto Negotiation Interrupt Control Register (Register 16) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
2 - 15 Reserved
Returns 0s
0 Always return zeros.
Interrupt
Status
1
Read/Write
If the interrupt is enabled, this bit will be asserted upon the completion of an
auto negotiation cycle; it will only be cleared by writing 0 to this bit. If the
interrupt is disabled, this bit will be set to 0. This is the auto negotiation
0
complete interrupt.
0 - interrupt is asserted
1 - interrupt is not asserted
0
Interrupt
Enable
Read/Write
1
0 - interrupt is disabled
1 - interrupt is enabled
Table 137 shows the Hard TEMAC Internal SGMII PCS Management Loopback Control Register bit definitions.
Table 137: SGMII Management Loopback Control Register (Register 17) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
1 - 15 Reserved
Returns 0s
0
Always return zeros.
Loopback
0 ^Position
Read/Write
Loopback is enabled or disabled using register 0 bit 14.
0
0 - loopback (when enabled) occurs directly before the interface to the
RocketIO transceiver
1 - loopback (when enabled) occurs in the RocketIO transceiver
Soft TEMAC Implementations
Introduction to Physical Interfaces
The soft TEMAC implementation is independent of, and can connect to, any type of physical layer device. The
XPS_LL_TEMAC provides additional circuitry around the soft TEMAC to allow easy use of two of the most
common physical layer device interfaces.
Because the soft TEMAC uses more logic and clock resources than a Hard TEMAC implementation, it is less likely
that multiple channels will be used in one device.
Please refer to Table 1 on page 4 for supported voltages with the different device families.
Media Independent Interface (MII)
The Media Independent Interface (MII), defined in IEEE 802.3 clause 22, is a parallel interface that connects at
10-Mb/S and/or 100-Mb/S to external PHY devices.
Please refer toUG138 LogicCORE IP Tri-Mode Ethernet MAC User Guide for an equivalent diagram of the clock
management scheme.
Soft TEMAC MII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
www.xilinx.com
137