DS537 Datasheet, PDF (59/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
TEMAC Unicast Address Word 1 (UAW1) Registers
The TEMAC Unicast Address Word 1 Register is shown in Figure 37. There is a separate register for each of the two
Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address
used to access the LSW and CTL registers.
The Unicast Addresses Registers combine to provide a 48 bit Ethernet station address. Word 0 provides the low
order 32 bits of the address while word 1 provides the high order 16 bits.
This register’s reset value is slightly different for implementations using the soft TEMAC (C_TEMAC_TYPE = 2),
Virtex-4 hard TEMAC (C_TEMAC_TYPE = 1), Virtex-5 hard TEMAC (C_TEMAC_TYPE = 0), and Virtex-6 hard
TEMAC (C_TEMAC_TYPE = 3).
X-Ref Target - Figure 37
15
0
Reserved
UnicastAddr(47:32)
DS537_37_091909
Figure 37: TEMAC Unicast Address Word 1 Registers (ADDRESS_CODE 0x384)
Table 36 shows the TEMAC Unicast Address Word 1 Registers bit definitions.
Table 36: TEMAC Unicast Address Word 1 Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
16 - 31 Reserved
Read ^0x0
Reserved. These bits are reserved for future definition and will
always return zero.
0 - 15
0x0000FFEE
0xFFFFFFFF ⁽¹⁾
UnicastAddr Read/Write
Unicast Address (47:32). This address is used to match against
the destination address of any received frames.
The address is ordered so the first byte transmitted/received is the
lowest positioned byte in the register; for example, a MAC address
of AA-BB-CC-DD-EE-FF would be stored in UnicastAddr(47:0) as
0xFFEEDDCCBBAA.
1. This register will return a different reset value for different TEMAC implementations. The soft TEMAC implementation will return a
0xFFFFFFFF while the Virtex-4 hard TEMAC, Virtex-5 hard TEMAC and Virtex-6 hard TEMAC implementations will return a
0x0000FFEE.
TEMAC Multicast Address Table Access Word 0 (MAW0) Registers
The TEMAC Multicast Address Table Access Word 0 Register is shown in Figure 38. There is a separate register for
each of the two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by
the address used to access the LSW and CTL registers.
The Multicast Addresses Table Access Word 0 and Word 1 registers combine to provide a 48 bit Ethernet addresses
to store in Multicast Address Table which can hold up to 4 addresses. (Filtering of more than 4 multicast addresses
can be achieved by including the extended multicast address function at build-time.) These two registers also
provide a place to store addresses being read from the Multicast Address Table.
Word 0 provides the low order 32 bits of the address while word 1 provides the high order 16 bits. Word 1 also
provides the table entry address and the read or write control signal. Figure 39 shows how word 0 and word 1
registers combine to make a Multicast Address Table entry.
The reset values stored in the 4 Multicast Address Table entries is slightly different for implementations using the
soft TEMAC (C_TEMAC_TYPE = 2), Virtex-4 hard TEMAC (C_TEMAC_TYPE = 1), Virtex-5 hard TEMAC
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