DS537 Datasheet, PDF (53/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 30 shows the TEMAC Transmit Configuration Registers bit definitions.
Table 30: TEMAC Transmit Configuration Registers Bit Definitions
Bit(s) Name
Core
Access
Reset
Value
Description
Reset. When this bit is "1", the transmitter is reset. The bit automatically resets
to "0". The reset also sets all of the transmitter configuration registers to their
31
RST
Read/Write
0
default values.
0 - no reset
1 - initiate a transmitter reset
Jumbo Frame Enable. When this bit is "1" the transmitter sends frames over
30
JUM⁽¹⁾ Read/Write
1
the maximum length specified in IEEE Std 802.3-2002 specification.
0 - send jumbo frames disabled
1 - send jumbo frames enabled
In-Band FCS Enable. When this bit is "1", the transmitter accepts the FCS field
with the rest of the frame data. When this bit is "0" the FCS field is calculated
29
FCS
Read/Write
0
and supplied by the transmitter. In either case the FCS field is verified.
0 - transmitter calculates and sends FCS field
1 - FCS field is provided with transmit frame data
Transmit Enable. When this bit is "1", the transmit logic is enabled to operate.
28
TX
Read/Write 1 0 - transmit disabled
1 - transmit enabled
VLAN Frame Enable. When this bit is "1", the transmitter allows transmission
27
VLAN⁽²⁾ Read/Write
of VLAN tagged frames.
1
0 - transmit of VLAN frames disabled
1 - transmit of VLAN frames enabled
Half-Duplex Mode. When this bit is "1", the transmitter operates in half-duplex
mode. When this bit is "0", the transmitter operates in full-duplex mode. Only
26
HD
Read/Write
0
full-duplex is supported so this bit should always be set to "0".
0 - full-duplex receive
1 - half-duplex receive (not supported)
Inter Frame Gap Adjustment Enable. When this bit is “1”, the transmitter uses
the value of the IFGP register (Figure 7, page 28) to extend the transmit Inter
Frame Gap beyond the minimum of 12 idle cycles (96-bit times on the Ethernet
25
IFG
Read/Write
1
Interface).
0 - no IFGP adjustment enabled
1 - IFGP adjusted based on IFGP register
0 - 24 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always return
zero.
1. Extended VLAN function require that jumbo frames be enabled (1).
2. This bit enables basic VLAN operation that is native to the TEMAC core. The TEMAC core recognizes VLAN frames when the
Type/Length field contains a VLAN TAG with a TPID value of 0x8100. No other TPID values are recognized. Extended VLAN mode
described later allow programmable TPID values. This bit must be ’0’ (disabled) when using extended VLAN mode.
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