DS537 Datasheet, PDF (86/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
X-Ref Target - Figure 54
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6
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Dest Srce Type
Addr Addr /Len
Data
FCS
Dest
Addr
Srce
Addr
VLAN
TAG
4 bytes
Type
/Len
Data
FCS
TPID
8100
9100
9200
88a8
16
bits
Priority VID
3 1 12
bits bit bits
DS537_54_091909
Figure 54: VLAN Frame Showing VLAN Tag Field
The TEMAC core provides basic VLAN support that can be enabled or disabled independently. This basic support
recognizes VLAN frames that have a TPID value of 0x8100. When basic VLAN function is enabled, the TEMAC core
will allow good VLAN frames with this TPID value to be processed for validation and address filtering rather than
being dropped.
However, some applications require using a TPID value other than 0x8100 or will have multiple VLAN tags within
one frame (referred to as double tagging, triple tagging, etc.). Additionally, some common operations are
performed on VLAN frames that can be off-loaded from software to hardware to reduce processor utilization. Some
of these tasks, translation, stripping, and auto tagging, are available when the extended VLAN support is included
in the core at build-time by setting the appropriate parameters.
The extended VLAN functions are available individually and independently between the transmit and receive
paths.
In order to use the extended VLAN functions, the circuitry must be included at build time by setting the
appropriate parameters and also the functions must be enabled at run time by setting the New Functions enable bit
(bit 20) of the Reset and Address Filter Registers (RAF0 and RAF1).
VLAN Translation
VLAN translation will enable the xps_ll_temac core to replace the VLAN ID (VID) value of the VLAN Tag field of
a VLAN frame with a new VID as it passes through the xps_ll_temac core in either the transmit or receive direction.
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