DS537 Datasheet, PDF (51/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 28 shows the TEMAC Receive Configuration Word 0 Registers bit definitions.
Table 28: TEMAC Receive Configuration Word 0 (RCW0) Registers Bit Definitions
Bit(s) Name
Core
Access
Reset Value
Description
31 - 0 PauseAddr
Read/Write
0xDDCCBBAA
Pause Frame Ethernet MAC Address (31:0). This address is used
to match the destination address of any received flow control frames.
It is also used as the source address for any transmitted flow control
frames.
This address is ordered so that the first byte transmitted/ received is
the lowest position byte in the register. For example, a MAC address
of AA-BB-CC-DD-EE-FF would be stored in the PauseAddr(47:0) as
0xFFEED-DCCBBAA.
TEMAC Receive Configuration Word 1 (RCW1) Registers
The TEMAC Receive Configuration Word 1 Register is shown in Figure 30. There is a separate register for each of
the two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers. These registers can be written at any time but the receiver logic
will only apply the configuration changes during Inter Frame gaps. The exception to this is the Reset bit which is
effective immediately.
X-Ref Target - Figure 30
JUM RX HD
31 30 29 28 27 26 25
15
0
RST FCS VLAN LT_DIS
Reserved
PauseAddr(47:32)
DS537_30_091909
Figure 30: TEMAC Receive Configuration Word 1 (RCW1) Registers (ADDRESS_CODE 0x240)
Table 29 shows the TEMAC Receive Configuration Word1 Registers bit definitions.
Table 29: TEMAC Receive Configuration Word1 (RCW1) Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
Reset. When this bit is "1", the receiver is reset. The bit automatically resets
to "0". The reset also sets all of the receiver configuration registers to their
31
RST
Read/Write
0
default values.
0 - no reset
1 - initiate a receiver reset
Jumbo Frame Enable. When this bit is "1" the receiver accepts frames over
30
JUM1⁽¹⁾
Read/Write
the maximum length specified in IEEE Std 802.3-2002 specification.
1
0 - receive jumbo frames disabled
1 - receive jumbo frames enabled
In-Band FCS Enable. When this bit is "1", the receiver provides the FCS
field with the rest of the frame data. When this bit is "0" the FCS field is
29
FCS
Read/Write
1
stripped from the receive frame data. In either case the FCS field is verified.
0 - strip the FCS field from the receive frame data
1 - provide the FCS field with the receive frame data
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