DS537 Datasheet, PDF (49/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 26: TEMAC Ready Status Register Ethernet Interface 0 Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
25
CFG_WR
Read
Configuration Register Write Ready Interface 0. This bit is set (ready)
when no configuration registers write operation is pending. Includes
1 ^{ADDRESS_CODE values of 0x200 - 0x340.}
0 - a configuration register write operation is in progress
1 - all pending configuration write operations are complete
16 - 24
Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
15 HARD_ACS_RDY Read
Hard register Access Ready Interface 0. This bit is set (ready) when
all other used bits in this Ready Status register are set.
1
0 - an access operation is in progress
1 - all pending access operations are complete
0 - 14
Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
TEMAC Ready Status Register Ethernet Interface 1 (RDY1)
The Ready Status Register is shown in Figure 28. This register is read only. The bits in the RDY register are asserted
when there is no access in progress. When an access is in progress, a bit corresponding to the type of access is
automatically de-asserted. The bit is automatically re-asserted when the access is complete.
X-Ref Target - Figure 28
HARD_ACS_RDY
AF_WR FABR_RR
CFG_WR
MIIM_WR
15
25 26 27 28 29 30 31
Reserved
Reserved
CFG_RR _{AF_RR} MIIM_RR
DS537_28_091909
Figure 28: Hard TEMAC Ready Status Register Ethernet Interface 1 (offset 0x06C)
Table 27 shows the TEMAC Ready Status Register Ethernet Interface 1 bit definitions.
Table 27: TEMAC Ready Status Register Ethernet Interface 1 Bit Definitions
Bit(s) Name
Core
Access
Reset
Value
Description
31 FABR_RR
Read
Fabric Read Ready Interface 1. This bit is set (ready) when no fabric based
registers read operation is pending. Includes ADDRESS_CODE values of
0x000 - 0x02F and 0x040 - 0x04F. These address ranges are not currently
1
supported.
0 - a fabric register read operation is in progress
1 - all pending fabric read operations are complete
30 MIIM_RR
Read
MII Management Read Ready Interface 1. This bit is set (ready) when no MII
Management registers read operation is pending. Corresponds to
1
ADDRESS_CODE 0x3B4.
0 - a MIIM register read operation is in progress
1 - all pending MIIM read operations are complete
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