DS537 Datasheet, PDF (126/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Loopback can be enabled or disabled by writing to the 1000BASE-X Management Control Register bit 14 (Table 124
on page 132) while the loopback position can be controlled by writing the 1000BASE-X Management Loopback
Control Register bit 0 (Table 98 on page 116).
Internal 1000BASE-X PCS/PMA Management Registers
Registers 0 through 15 are defined in IEEE 802.3. These registers contain information relating to the operation of the
1000BASE-X PCS/PMA sublayer, including the status of the physical Ethernet link (PHY Link).
Additionally, these registers are directly involved in the operation of the 1000BASE-X auto negotiation function
which occurs between the XPS_LL_TEMAC and its link partner, the Ethernet device connected at the far end of the
PHY Link.
These registers are accessed via the MII Management interface (see "Using the MII Management to Access Internal
or External PHY Registers" on page 67). These registers are only valid when using the 1000BASE-X PHY interface.
When using 1000BASE-X, the XPS_LL_TEMAC is typically connected to an external optical transceiver device such
as a GBIC or SFP transceiver.
Table 112: Internal 1000BASE-X PCS/PMA Management Registers
Register Name
Control Register (Register 0)
Status Register (Register 1)
PHY Identifier (Register 2 and 3)
Auto Negotiation Advertisement Register (Register 4)
Auto Negotiation Link Partner Ability Base Register (Register 5)
Auto Negotiation Expansion Register (Register 6)
Auto Negotiation Next Page Transmit Register (Register 7)
Auto Negotiation Next Page Receive Register (Register 8)
Extended Status Register (Register 15)
Vendor Specific Register: Auto Negotiation Interrupt Control Register (Register 16)
Vendor Specific Register: Loopback Control Register (Register 17)
Register Address
(REGAD)
0
1
2,3
4
5
6
7
8
15
16
17
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