DS537 Datasheet, PDF (29/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 11 shows the Transmit Inter Frame Gap Adjustment Register bit definitions.
Table 11: Transmit Inter Frame Gap Adjustment Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
24 - 31 IFGP0
Read/Write
Transmit Inter Frame Gap Adjustment Value. This 8-bit value can be used
along with the Inter Frame Gap Adjustment Enable bit of the Transmit
Configuration Register (See "TEMAC Control Register Bit Definitions" on
0x0
page 47.) to increase the Transmit Inter Frame Gap. This value is the width
of the IFG in idle cycles. Each idle cycle is 8 bit times on the Ethernet
interface. The minimum IFG time is 12 idle cycles which is 96 bit-times. If this
field value is less than 12 or if IFGP adjustment is disabled in the Transmit
Configuration register, an IFGP of 12 idle cycles (96-bit times) will be used.
0 - 23 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Interrupt Status Registers (IS0 and IS1)
The Interrupt Status Register is shown in Figure 8. This register combined with the IE, IP, TIS, and TIE registers
define the interrupt interface of the XPS_LL_TEMAC. The Interrupt Status register uses one bit to represent each
XPS_LL_TEMAC internal interruptible condition. One of these interruptible conditions, Hard register Access
Complete (HardAcsCmplt), comes from the TEMAC component and is further defined and enabled by the TIS and
TIE registers which will be described later in this document. A separate IS register exists for TEMAC interface 0 and
TEMAC interface 1.
Once an interruptible condition occurs, it will be captured in this register (represented as the corresponding bit
being set to 1) even if the condition goes away. The latched interruptible condition is cleared by writing a 1 to that
bit location. Writing a 1 to a bit location that is 0 has no effect. Likewise, writing a 0 to a bit location that is 1 has no
effect. Multiple bits may be cleared in a single write.
For any bit set in the Interrupt Status Register, a corresponding bit must be set in the Interrupt Enable Register for
the same bit position to be set in the Interrupt pending register. Whenever any bit are set in the Interrupt Pending
Register, the TemacIntc_Irpt signal is driven active high out of the XPS_LL_TEMAC. Figure 9 shows the structure of
the interrupt registers.
X-Ref Target - Figure 8
RxFifoOvr HardAcsCmplt
RxDcmLock _RxCmplt
24 25 26 27 28 29 30 31
Reserved
TxCmplt AutoNeg
MgtRdy
RxRject
DS537_08_091909
Figure 8: Interrupt Status Registers (offset 0x00C and 0x04C)
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