DS537 Datasheet, PDF (124/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
RocketIO transceiver across the SGMII Link. This transfers the results of the PHY with Link Partner auto
negotiation across the SGMII to the XPS_LL_TEMAC.
The results of the SGMII auto negotiation can be read from the SGMII Management Auto negotiation Link Partner
Ability Base Register (Table 131). The duplex mode and speed of the XPS_LL_TEMAC should then be set to match
(see "TEMAC Receive Configuration Word 1 (RCW1) Registers" on page 51, "TEMAC Transmit Configuration (TC)
Registers" on page 52, and "TEMAC Ethernet MAC Mode Configuration (EMMC) Registers" on page 54).
There are two methods that may be used to learn of the completion of an auto negotiation cycle:
• By polling the auto negotiation complete bit of SGMII Management Status Register (Register 1, bit 5 Table 127).
• By using the auto negotiation complete interrupt (see "Interrupt Status Registers (IS0 and IS1)" on page 29 and
SGMII Management Auto Negotiation Interrupt Control Register Table 136 on page 137.)
Loopback
There are two possible loopback positions:
• Loopback in the Hard TEMAC silicon component. When placed into loopback, data is routed from the
transmitter to the receiver path at the last possible point in the PCS/PMA sublayer. This is immediately before
the RocketIO transceiver interface. When placed into loopback, a constant stream of Idle code groups is
transmitted through the RocketIO transceiver. Loopback in this position allows test frames to be looped back
within the system without allowing them to be received by the link partner (the device connected on the other
end of the Ethernet. The transmission of Idles allows the link partner to remain in synchronization so that no
fault is reported.
• Loopback in the RocketIO transceiver. The RocketIO can be switched into loopback and will route data from
the transmitter path to the receiver path within the RocketIO transceiver. However, this data is also transmitted
out of the RocketIO transceiver and so any test frames used for a loopback test will be received by the link
partner.
Loopback can be enabled or disabled by writing to the SGMII Management Control Register bit 14 (Table 126 on
page 133) while the loopback position can be controlled by writing the SGMII Management Loopback Control
Register bit 0 (Table 137 on page 137).
1000BASE-X PCS/PMA
Please refer to the UG074 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide v1.9 for an equivalent diagram
of the clock management scheme.
PCS/PMA
The Physical Coding Sublayer (PCS) for 1000BASE-X operation is defined in IEEE 802.3 clause 36 and 37 and
performs the following:
• Encoding (and decoding) of GMII data octets to form a sequence of ordered sets
• 8B/10B encoding (and decoding) of the sequence ordered sets
• 1000BASE-X Auto-Negotiation for information exchange with the link partner
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