DS537 Datasheet, PDF (14/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 3: I/O Signal Description
Signal Name
Interface
Signal
Type
Init
Status
Description
RGMII_TXD_1(3:0)
Ethernet bus
1 RGMII
O
0
TEMAC to PHY transmit data
RGMII_TX_CTL_1
Ethernet bus
1 RGMII
O
0
TEMAC to PHY transmit control
RGMII_TXC_1
Ethernet bus
1 RGMII
O
0
TEMAC to PHY transmit clock
RGMII_RXD_1(3:0)
Ethernet bus
1 RGMII
I
PHY to TEMAC receive data
RGMII_RX_CTL_1
Ethernet bus
1 RGMII
I
PHY to TEMAC receive control
RGMII_RXC_1
Ethernet bus
1 RGMII
I
PHY to TEMAC receive clock
Ethernet Channel 0 MII Management Interface (MIIM) Signals
MDC_0
Ethernet bus
0 MIIM
O
0
TEMAC to PHY MII management
bus clock
MDIO_0
Ethernet bus
0 MIIM
I/O
0
TEMAC to/from PHY MII
management data
Ethernet Channel 1 MII Management Interface (MIIM) Signals
MDC_1
Ethernet bus
1 MIIM
O
0
TEMAC to PHY MII management
bus clock
MDIO_1
Ethernet bus
1 MIIM
I/O
0
Host Read External Data Interface Signals⁽⁶⁾
TEMAC to/from PHY MII
management data
HostMiimRdy
Host Read
I
External Data to TEMAC read ready
HostRdData(31:0)
Host Read
I
External Data to TEMAC read data
HostMiimSel
Host Read
O
0
TEMAC to External Data Enable
HostReq
Host Read
O
0
TEMAC to External Data Read
Request
HostAddr(9:0)
Host Read
O
0
TEMAC to External Data Read
Address
HostEmac1Sel
Host Read
O
0
TEMAC to External Data TEMAC 0
vs. TEMAC1 select
Ethernet Statistics Interface Signals
TxClientClk_0
Statistics 0
O
0
TEMAC to Statistics TX Clock
ClientTxStat_0
Statistics 0
O
0
TEMAC to Statistics TX Data
ClientTxStatsVld_0
Statistics 0
O
0
TEMAC to Statistics TX Valid
Indicator
ClientTxStatsByteVld_0
Statistics 0
O
0
TEMAC to Statistics TX Byte Valid
Indicator
RxClientClk_0
Statistics 0
O
0
TEMAC to Statistics RX Clock
ClientRxStats_0(6:0)
Statistics 0
O
0
TEMAC to Statistics RX Data
ClientRxStatsVld_0
Statistics 0
O
0
TEMAC to Statistics RX Valid
Indicator
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