DS537 Datasheet, PDF (54/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
TEMAC Flow Control Configuration (FCC) Registers
The TEMAC Flow Control Configuration Register is shown in Figure 32. There is a separate register for each of the
two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers. These registers can be written at any time but the flow control
logic will only apply the configuration changes during Inter Frame gaps.
X-Ref Target - Figure 32
FCTX
30 29
Reserved
FRTX
Reserved
ds537_32_091909
Figure 32: TEMAC Flow Control Configuration Registers (ADDRESS_CODE 0x2C0)
Table 31 shows the TEMAC Flow Control Configuration Registers bit definitions.
Table 31: TEMAC Flow Control Configuration Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
31
Reserved
Read
0
Reserved. These bits are reserved for future definition and will always
return zero.
Transmit Flow Control Enable. When this bit is “1”, the transmitter will
send a flow control frame when a value is written to the TPF register
30
FCTX
Read/Write
1 ^{(page 28).}
0 - transmit flow control frame disabled
1 - transmit flow control frame enabled
Receive Flow Control Enable. When this bit is "1", the receive flow control
frames inhibit transmitter operation. When this bit is "0", the flow control
29
FCRX
Read/Write
1
frames are passed through with other receive frames.
0 - receive flow control disabled
1 - receive flow control enabled
0 - 20 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
TEMAC Ethernet MAC Mode Configuration (EMMC) Registers
The TEMAC Ethernet MAC Mode Configuration Register is shown in Figure 33. There is a separate register for each
of the two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers. These registers can be written at any time but the Ethernet
interface will only apply the configuration changes during Inter Frame gaps. This register is slightly different for
implementations using the soft TEMAC (C_TEMAC_TYPE = 2), Virtex-4 hard TEMAC (C_TEMAC_TYPE = 1),
Virtex-5 hard TEMAC (C_TEMAC_TYPE = 0), and Virtex-6 hard TEMAC (C_TEMAC_TYPE = 3)
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