UPD78F9500MA-CAC-A Datasheet, PDF (98/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY)
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FF60H After reset: 00H R/W
Symbol 7
6
5
4
3
2
1 <0>
TMC00 0
0
0
0 TMC003 TMC002 TMC001 OVF00
TMC003 TMC002 TMC001
Operating mode and clear
mode selection
0
0
0 Operation stop
0
0
1
(TM00 cleared to 0)
0
1
0 Free-running mode
0
1
1
1
0
0 Clear & start occurs on valid
1
0
1
edge of TI000 pin
1
1
0 Clear & start occurs on match
between TM00 and CR000
1
1
1
TO00 inversion timing selection Interrupt request generation
No change
Not generated
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
−
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
< When operating as compare
register >
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
< When operating as capture
register >
Generated on TI000 pin and
TI010 pin valid edge
OVF00
0 Overflow not detected
1 Overflow detected
Overflow detection of 16-bit timer counter 00 (TM00)
Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.
2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to
the TI000/TI010 pins.
3. Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before
setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the
system clock starts.
4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after
stopping the timer operation.
5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the
valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is
FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes
0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is
disabled.
7. The capture operation is performed at the fall of the count clock. An interrupt request input
(INTTM0n0), however, occurs at the rise of the next count clock.
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User’s Manual U18172EJ3V0UD