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| UPD78F9500MA-CAC-A Datasheet, PDF (289/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers | |||
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CHAPTER 18 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
MOVW
rp, #word
3
AX, saddrp
2
saddrp, AX
AX, rp
rp, AX
2
Note
1
Note
1
XCHW
AX, rp
Note
1
ADD
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
ADDC
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
SUB
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
Note Only when rp = BC, DE, or HL.
6 rp â word
6 AX â (saddrp)
8 (saddrp) â AX
4 AX â rp
4 rp â AX
8 AX â rp
4 A, CY â A + byte
6 (saddr), CY â (saddr) + byte
4 A, CY â A + r
4 A, CY â A + (saddr)
8 A, CY â A + (addr16)
6 A, CY â A + (HL)
6 A, CY â A + (HL + byte)
4 A, CY â A + byte + CY
6 (saddr), CY â (saddr) + byte + CY
4 A, CY â A + r + CY
4 A, CY â A + (saddr) + CY
8 A, CY â A + (addr16) + CY
6 A, CY â A + (HL) + CY
6 A, CY â A + (HL + byte) + CY
4 A, CY â A â byte
6 (saddr), CY â (saddr) â byte
4 A, CY â A â r
4 A, CY â A â (saddr)
8 A, CY â A â (addr16)
6 A, CY â A â (HL)
6 A, CY â A â (HL + byte)
Flag
Z AC CY
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Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
Userâs Manual U18172EJ3V0UD
287
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