UPD78F9500MA-CAC-A Datasheet, PDF (85/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 5 CLOCK GENERATORS
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation
clock operates as the system clock.
Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation
Power
application
VDD > 2.1 V ±0.1 V
Reset by
power-on clear
Reset signal
High-speed internal
oscillator selected
by option byte
Start with PCC = 02H,
PPCC = 02H
Interrupt
HALT
Clock division ratio
variable during
CPU operation
HALT
instruction _STOP
instruction
Interrupt
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
User’s Manual U18172EJ3V0UD
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